Adjusting Transistor Length, Editing Models & Finding Small Signal Parameters. Unfortunately, when you change W and L in the PSPICE MOSFET Level 1 Model (the one we are using) it adjusts

some but not all of the spice parameters in the correct manner. Changing W First and easiest to deal with is the area of the source and drain regions. The picture below shows a view of a MOSFET from above. AS is the area of the source and AD is the area of the drain in meters. In the PSPICE model AS and AD remain at their default value as the width is changed, which is incorrect. To fix this I revised the Capture Part to explicitly show AD and AS on the schematic. The areas given for the default 5 micron wide FETs now can be manually changed as you scale the width. For us Ldiff (E in the textbook) will be taken to be 1.5x10 meters (1.5 um) and to remain constant for all transistors. The areas will then be given by AS = AD=1.5x10 x W m². When changing transistor widths, you will need to compute these areas and enter them on the schematic to be passed to the SPICE model. These areas will not be affected by changing L. The good news is that these areas mainly influence the source-bulk and drain-bulk capacitances, they have no effect on currents. So unless you are doing a transient simulation, a frequency sweep or any in which these capacitances matter your answers will still be correct, but I would get in the habit of changing them anyway just so as not to forget, but you don't need to fiddle with them when you are trying to find the DC gain or set up bias conditions. NRS-N(source) PS= 2 x L (source) + W Lag (source) → AS-WXL (source) NRD=N(drain) PD=2x Lag (drain) + W Lag (drain) AD=WxLag (drain)/nThe situation is worse for adjustments to L, the good news is that often you will want to use the minimum length transistor as for the most part these give the best performance; highest speed, best gm for a given drain current etc. However sometimes like for current sources or cascoding transistors among other applications you would like to have transistors with a higher output resistance, ro. You can obtain a higher ro by increasing L. The problem here is that the built-in PSPICE MOSFET model we are using does not change the model parameter LAMBDA as it should. For these 0.5 um long device models Lambda is fixed at 0.1 irrespective of the gate length. It should scale like: where for the NFETs C=0.034 and for the PFETs C=0.064. Lambda=- с с Leff L-2LD These values for C are used so that we get the correct value of LAMBDA for the 0.5 μm long devices. Once you have the correct value of LAMBDA to use with the length that you have chosen you then need to edit the SPICE model for those devices which have the longer length. The next section will describe how to edit the SPICE model for individual transistors in your design. Note: If you want to change the ro of a transistor but not mess with its ID or VGs you can increase W by the same factor that you increased L. That keeps the W/L ratio constant and the ID current equation mostly unchanged. There is another wrinkle about which you should be aware. In saturation we use the formular, 1 AID 1+2 Vps. So, there will MID The MOSFET model equations implemented in PSPICE user= be a small disagreement for devices with a high VDs between hand calculations and SPICE unless you use the same formula that SPICE uses for your hand calculation. Model Editor The model editor is useful for more that just getting the effect of length changes correct. For instance, I used it to set GAMMA to zero in order to turn off the body effect for one of the homework solutions. To open the model editor select the transistor whose model you wish to change. Once selected, it changes color, then right click on the transistor. One of the options that show up in the context menu is "Edit PSPICE Model". Clicking on that opens the model editor. In the text box with the model parameters change the parameters that you wish to adjust. If you choose save then the model is saved in your local design library located in PSpice Resources>Model Libraries in your project Hierarchy on the first page of your project./nI change the model for every transistor that uses that original model in your design. To change the model for only the selected transistor you need to give it a new name. To do this change the name in the text box in the model editor before saving. Here is an example. The original model statement; .MODEL NFET4 NMOS would be edited for example to .MODEL NFET4-L10u NMOS. Now when saved the new model is still saved to your local design library but will apply to only the transistor that you originally clicked on and show up in the left panel of the Model editor with the new name. To use it elsewhere you can then just copy and paste the transistor on your schematic. This sometimes will not update the model name that appears on your schematic. To check which model a FET uses you can select and right click on a transistor and choose "Edit Properties". The Model name that will be used in the simulation is listed in the properties table next to "Implementation". This is all rather poorly documented in the PSPICE help files and manual so I hope that this is clear. Operating Point Here we will look at the effect of length changes on the output resistance of our NFET. Perform a bias point analysis for NFETs with gate lengths of 0,5, 1 and 2 microns. For the L=0.5 µm transistor use a width of 5 μm. Choose the widths of the other transistors so that all 3 transistors have the same W/L ratio. Bias their gates with 200 mV of overdrive and set the drain voltages to 3V. In the Simulation Settings be sure to check the "Include detailed bias point information for nonlinear controlled sources and semiconductors (OP)" option. This will save the small signal model for each transistor to the output file. Once the simulation runs view the Output file in the probe window. Toward the end you will see the list of your transistors and the small signal model parameters at the bias point for each. Copy this table into your report. It also lists the SPICE model parameters for each transistor, this is not what I want to see. Calculate the ro of each transistor to see the effect of the length change. I say calculate because SPICE does not report r, directly, rather it gives you the conductance between drain and source, GDS. In general, the bias point analysis is a good way to see what the small signal parameters are, especially for the parasitic capacitances which can be a bit tedious to calculate. It/non the schematic if you select the appropriate option buttons in the Capture toolbar. This analysis is most useful for setting up your desired bias points for designs. Sweep analysis of ro. Next for the same 3 transistors perform a DC Sweep analysis to generate the Ip vs VDS graph for each transistor. For ease of comparison graph them all on the same plot. Indicate the operating regions on your graph, any transition voltages and label each plot line with the transistor's gate length. Question: The VGs and W/L ratio is the same (or should be) for each transistor why do the curves look different? Explain. The slope of this graph at each point corresponds to the small signal drain-source conductance. Come up with a trace expression that will display to as a function of VDD. Plot ro for each transistor, all on the same plot. Note in particular what happens to ro when the devices enter triode. Often a graph like this will give you a better idea of what is going on than just looking at equations. Provide the equations for ro in each operating region and explain how they relate to your plot. Is your plot reasonable does it qualitatively agree with your plots? This last bit is sort of a check on your simulation, you always need to ask yourself if the SPICE results are reasonable, it is easy to make simulation errors. Provide: Source files PSICE Orcad 16.6 Simulation schematic for Bias point Operating Point Table Calculated Output resistances Simulation schematic for ID vs VDS plot, if different from that above. ID VS VDS Plot Question response To VS VDS plot. ro equations and comparison