Applied Electronics (UFMFHT-30-1) VHDL for Sequential Circuits Lab Objectives Upon completion of this lab, you should be able to 1. Use VHDL Sequential Statements to Implement D Flip Flops. 2.

Use Different Approaches to Implement Synchronous Counters. Equipment 1. Quartus Prime 2. DE0-CV Development Board (Figure 1) 3. USB Cable Allocated Time: 2 hours OO MER TEXAS Panasonic 28.8.8.8.8.8. Lab 7 - VHDL for Sequential Circuits A DEO-CV Cyclone terasIC ADERA. ISSI gggg 12:0 10 29 30 OF 10 1 Figure 1: DE0-CV Development Board $::::::: Year 2023/2024 Lab 7 Page 1 Applied Electronics (UFMFHT-30-1) I. Background I.1 Sequential Statements: I.1.1 "Process" Statement A process is a set of sequential instructions executed in a predefined order. A process has a name, which is optional. A process has a sensitivity list. The execution of statements takes place in response to changes of the signals in the sensitivity list. The sequence of statements is sequentially evaluated. The syntax of the process statement is shown in figure 2. I.1.2. "if" Statement [name:] process (sensitivity_list) Declarations; I.1.3. "case" Statement sequence-of-statements; end process; Figure 2: The "Process" Statement In VHDL, "if" is a statement that is used to conditionally execute at least one sequential statement. The execution depends on a certain condition. It is possible to nest statements, controlled by different conditions using "elseif" branches (or "else if"). While the number of "elseif" is unlimited, there is only one "else" branch. The “else" branch is the last instruction and comes at the end before the "elseif" statement. What comes between the square brackets [ ] is optional. The syntax of the “if” statement is shown in figure 3. begin if (condition1) then Sequence_of_statements; [elsif (condition2) then Sequence_of_statements; elsif (condition3) then else Sequence_of_statements; endif; [Sequence_of_statements]; Lab 7 - VHDL for Sequential Circuits .] Year 2023/2024 Figure 3: The "if" Statement Depending on the value of an associated expression, the "case" statement selects for execution one of several alternative sequences of statements. The syntax of the case statement is shown in figure 4. Page 2 Applied Electronics (UFMFHT-30-1) case expression is when choice => sequential_statement; when choice => sequential_statement; when choice => sequential_statement; end case; Figure 4: The "Case" Statement I.2 Implementing Sequential Circuits Using VHDL I.2.1 Clocked D Flip Flops A D flip flop, as illustrated in figure 5, has two synchronous inputs D and Clk (clock) and two asynchronous inputs PRN (set) and CLRN (reset). The outputs of the flip flop are Q and Q (inverted output), respectively. The operation of a D flip flop is very simple and is illustrated in Table 1. When the asynchronous inputs are HIGH (PRN = 1 and CLRN = 1) and at the positive transition of the clock signal, the input is assigned to the output (Q = D). The flip flop is reset when PRN 1 and CLRN = = 0. The flip flop is set when PRN = 0 and CLRN = 1. D D 0 1 Lab 7 - VHDL for Sequential Circuits O PRN Clk Q CLRN Figure 5: D clocked Flip Flop Clk Q ↑ ↑ 1 Table 1: Truth Table of a D Flip Flop Year 2023/2024 The VHDL code that implements a simple D flip flop is shown in figure 6. Notice that the two asynchronous inputs PRN (Set) and CLRN (Clear) have been ignored in the VHDL description - as well as the inverted output -. Page 3 Applied Electronics (UFMFHT-30-1) library ieee; use ieee.std_logic_1164.all; entity Dflipflop is port ( clock, D in std_logic; : out std_logic); Q end entity; architecture ff of Dflipflop is begin process (clock) begin if (clock = '1' and clock'event) then Q <= D; end if; end process; end ff; Figure 6: VHDL Implementation of D Flip Flop The VHDL de ription of figure 6 could be easily expanded to include both asynchronous inputs and the inverted output, respectively. The code could be then used as a building block (component) in structural VHDL models to implement shift registers and counters. I.2.2. Synchronous Counters In both Lecture 6 and Lab 6, the methodology for designing synchronous counters using JK flip flops has been introduced. In synchronous counters, the flip flops are simultaneously clocked using the same clock signal. Figure 7 shows the state transition diagram of a MOD 5 synchronous counter as introduced in both lecture 6 and lab 6. 110 111 101 Lab 7 - VHDL for Sequential Circuits ............ Qo Q₁ Q₂ 000 100 001 011 010 Year 2023/2024 Figure 7: State Transition Diagram of the 3-bit MOD 5 Synchronous Counter The digital circuit that implements the MOD 5 counter is illustrated in figure 8. Page 4 Applied Electronics (UFMFHT-30-1) Clock Q₂ Q₁ J Clk '1' K Qo begin library ieee; use ieee.std_logic_1164.all; Qo entity Syncount5 is port (clock: in std_logic; Q end Syncount5; Qo+Q₂ Figure 8: 3-bit MOD 5 Synchronous Counter J Clk Q <= count; end count5; K architecture count5 of Syncount5 is end process; Q Lab 7 - VHDL for Sequential Circuits Q₁ Using sequential statements such process, case and if, different VHDL implementations could be envisaged. Two of such implementations are illustrated in figure 9 and figure 10, respectively. : out std_logic_vector (2 downto 0)); process (clock) variable count: std_logic_vector (2 downto 0); begin if (clock = '1' and clock'event) then case count is when "000" => count := "001"; => count := "010"; when "001" when "010" => count := "011"; when "011" => count := "100"; when "100" => count := "000"; when others => count :="000"; end case; end if; '1' Figure 9: VHDL Description of a MOD 5 Synchronous Counter using "process" and "case" Statements J Year 2023/2024 Clk K 2₂ Page 5