Assignment 1: Consider the following instructions given below. I1: Add R1, R2, R3 12: Add R2, R1, R4 13: Add R1, R1, R4 These instructions are executed in a computer that has a five-stage pipeline as described in Chapter 6. The first instruction is fetched is clock cycle 1. The clock period for the pipelined processor is specified below for the processor with and without forwarding logic. Forwarding With Forwarding Clock Period 100 psec Without Forwarding 150 psec (a) Identify the data dependencies and their type (i.e. RAW, WAR, and WAW). For example, use the format: 14 →> 12, Register RO, RAW. To identify a RAW data dependency between instructions 12 and 14 due to register RO. (b) Assume that there is NO forwarding logic in the processor. Identify the RAW data hazards. For example, use the format: 13 →12, Register R4. To identify a RAW data hazard between instructions 12 and 13 due to register R4. (c) Assume that there is forwarding logic in the processor. Identify the RAW data hazards. Use the same format described above. (d) What is the total execution time (ET) of this code segment on the processor without forwarding logic and with forwarding logic? What is the speedup achieved by adding forwarding logic to a pipeline that did not have it? i. Without forwarding logic: You can use the flowing diagram to calculate the total clock cycles : Cycle Add R1, R2, R3 1 2 3 F D Add R1, R2, R3 Or: use the flowing table: IF ID EX MEM WB 1 I1 2 3 4 5 6 7 8 9 10 11 ii. With forwarding logic:

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assignment 1 consider the following instructions given below i1 add r1

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Assignment 1: Consider the following instructions given below. I1: Add R1, R2, R3 12: Add R2, R1, R4 13: Add R1, R1, R4 These instructions are executed in a computer that has a five-stage pipeline as described in Chapter 6. The first instruction is fetched is clock cycle 1. The clock period for the pipelined processor