Assignment 2: Consider the following instructions at the given addresses in the memory: 0x0000.1000 Load R1, 0(RO) 0x0000.1004 Add R2, R1, #5 0x0000.1008 And R3, R2, #0x0000.0010 0x0000.100C Store R3, 4(R4) 0x0000.1010 Add R5, R2, R3 Initially, RO and R4 contain 0x0000.2000 and Ox1000.2000, respectively. These instructions are executed in a computer that has a five-stage pipeline as described in Chapter 6. The first instruction is fetched in clock cycle 1. (a) Assume all memory access operations are cache hit. Complete the diagram that represents the flow of the instructions through the pipeline. How many cycles does it take to execute all the instructions if data forwarding is allowed? Also add marks to the diagram to indicate where data forwarding is used. Cycle 1 2 3 Load R1, 0(RO) F D... Add R2, R1, #5 F And R3, R2, #0x0000.0010 Store R3, 4(R4) Add R5, R2, R3 (b) Assume only memory accesses to addresses 0x1000.0000-0x3000.0000 are cache hit. Accesses to all other addresses are cache miss, which take 3 cycles to complete. Repeat Problem (a) to draw a diagram that represents the flow of the instructions through the pipeline. How many cycles does it take to execute all the instructions if data forwarding is allowed? Also add marks to the diagram to indicate where data forwarding is used.