B) In a system on a chip with 1 billion transistors, the subthreshold leakage of OFF transistors for off transistors is 100nA/um for a low threshold devices and 10nA/um for high threshold devices. The gate leakage is 5nA/um. Junction leakage is negligible. Memories use low- leakage devices everywhere. Logic uses low-leakage device in all but 5% of the paths that are most critical performance.The process used is 1.2 V - 65 nm, n =25 nm, 100 million transistors are in logic gates and rest in memory arrays. The average logic transistor width is 12% and the average memory transistor width is 4 2. The memory arrays are divided into banks and only the necessary bank is activated so the memory activity factor is 0.02. The static CMOS logic gates have an average activity factor of 0.1. Each transistor contributes 1 fF/um of gate capacitance and 0.8 fF/um of diffusion capacitance. a) Estimate the switching power when operating at 1 GHz frequency. b) Estimate static power consumption.

Solved: B) In a system on a chip with 1 billion transistors, the subthreshold

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B) In a system on a chip with 1 billion transistors, the subthreshold leakage of OFF transistors for off transistors is 100nA/um for a low threshold devices and 10nA/um for high threshold devices. The gate leakage is 5nA/um. Junction leakage is negligible. Memories use low- leakage devices everywhere. Logic uses low-l