(d) Ins (e) 1.5 ps 3.4 Compute the clock frequency for the following clock periods. (a) 500 ms (b) 400 n (c) 4 ns (d) 20 ps 3.5 Trace the behavior

of an SR latch for the following situation: Q, S, and R have been 0 for a long time, then S changes to 1 and stays 1 for a long time, then S changes back to 0. Using a timing diagram, show the values that appear on wires S. R. t, and Q. Assume logic gates have a tiny nonzero delay. 3.6 Repeat Exercise 3.5, but assume that 5 was changed to 1 just long enough for the signal to propagate through one logic gate, after which S was changed back to 0-in other words, S did not satisfy the hold time of the latch. 3.7 Trace the behavior of a level-sensitive SR latch (see Figure 3.16) for the input pattern in Figure 3.94. Assume S1, R1, and Q are initially 0. Complete the timing diagram, assuming logic antes have a time but nonem delay