Design an n-channel Silicon JFET with a Pinch off voltage of -20 V with following

constraints:

Gate width = 0.1 cm

Use only Phosphorous or Born dopants

Physical design parameters must be reasonable and feasible for JFET fabrication

Hand Calculations:

a) Must tabulate all parameters obtained, the device geometry as well as any other

unknown parameters such as the channel thickness, channel length, doping densities,

carriers' mobility, built-in potential, and turn off voltage (VŢ).

b) Calculate substrate's resistance used.

c) Calculate IDsat and VDsat for VG at 0 V, -5 V, -10 V, -15 V, must tabulate.