ECE 2020 Simulation Based Lab 2 DIGITAL FSM CIRCUIT MODELING AND SIMULATION WITH MULTISIM Multisim is a schematic capture and simulation program for analog, digital and mixed analog/digital circuits, and is one application program of the National Instruments "Circuit Design Suite", which also includes printed circuit board design tools and an interface to the ELVIS breadboarding platform. In this simulation-based lab, we will be using Multisim to perform simulations of digital circuits. Before getting started on the lab, we need to accomplish two tasks. 1. Install Multisim 2. Complete the Pre-lab assignments. Once you have installed Multisim and completed the Pre-Lab assignment, we will work on modeling and analyzing digital finite state machine (FSM) circuits using Multisim. The basic steps in modeling and analysis of a FSM circuits are: 1. Open Multisim and create a "design". 2. Draw a schematic diagram of the circuit (components and interconnections). 3. Define digital test patterns to be applied to the circuit inputs to simulate the circuit and connect signal sources to the inputs to produce these patterns. 4. Connect the circuit outputs to one or more indicators to display the response of the circuit to the test patterns. 5. Run the simulation and examine the results, copying and pasting Multisim windows into lab reports and other documents as needed. 6. Save the design. 1. Installing Multisim See separate document that was posted with Lab 1 on installing MULTISIM/LABVIEW. In ECE 2020, we will use MULTISIM only. 2. Tutorial on Multisim Please refer to the Multisim tutorial from Lab1. We are going to use the same techniques in this lab as well. 1 3. Pre-lab Assignment (Complete your work on a separate document and upload along with your lab work) Background: States: A = 00, B = 01, C = 10, D =11 where the states are defined by the values stored in the registers; for example, State B corresponds to S1S0 = 01 where S1 is the value of Register 1 and S0 is the value of Register 0. The next state for values of the registers is defined by NSI for Register i. For example, if the current state is B and the next state is C, then S1S0 = 01 and NS1 = 1 and NS0 = 0. External input: The external input in this circuit is denoted as "X". 3-to-8 Decoder with non-inverting inputs: Signals A0 - A2 represent the inputs and Y0 - Y7 represent the outputs. The convention is that A2 represents the most significant bit of a binary number and A0 represents the least significant bit; for example, an input of 011 is designated as A2A1A0 = 011. 2 Yo Ao Y1 A1 3 to 8 Y2 decoder Y4 Y3 A2 Y5 Y6 Y7 Fig. 1 (a): 3x8 Decoder with non-inverting outputs 3-to-8 Decoder with inverting inputs: The 74138 decoder (that you can find in your actual kit) has inverted outputs, so in the Pre-lab as well as the Multisim Lab, we are going to use a decoder with inverting outputs. YOO A0 Y1 A1 Y2 A2 Y3 b- Y40 Decoder Y5 16 Fig. 1 (b): 3x8 Decoder with inverting outputs 2 PRE-LAB PROBLEMS 1) Fill out the state transition table for the given state machine: X=0 A X=1 B (00) (01) X=0 + X=1 X=1 X=0 X=0 D C (11) X=1 (10) 3 STATE S1 So X NEW STATE |NS1 NSo A 0 0 0 A 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 3 2) Draw the circuit for your state machine below using Decoders and 2-input NAND gates as well as Flip-Flops. It is mandatory to use a Decoder whose outputs are inverted. Remember that decoders using inverted outputs and NANDs are functionally the same as decoders using non- inverted outputs and ORs. 4 4. MULTISIM portion of the Lab. Lab (1): Building a 3-state FSM. a) The state transition diagram for this state machine is shown in Figure 2. 5 5 X=1 A (00) X=1 X=0 X=1 C B (10) X=0 (01) X = 0 Fig. 2: State Transition Diagram for an example FSM. b) The state-transition table is shown below: A 0 0 0 B 0 1 A 0 0 1 A 0 0 State S1 So X New State 1 0 1 0 NS NS0 B 0 1 1 A 0 0 A 0 0 1 C 1 0 0 C 1 0 A 0 0 1 1 A 0 0 0 0 B 0 1 1 1 0 0 C 1 0 B 0 1 1 A 0 0 1 1 C 1 0 0 C 1 0 C 1 0 1 A 0 0 -- 1 1 0 -- -- -- -- 1 1 1 -- -- -- 5 c) The schematic below in Figure 3 shows the corresponding circuit. Input (X) So A0 YO D A1 Y1 To output probe A2 Y3 Y4 Y2 CLK D flip flop Decoder Y5 To output probe D C Y7 S1 D flip flop CLK Fig. 3: Circuit Diagram for Example State machine d) Implement the circuit in Fig. 3 using components in Multisim. You can use the techniques from Lab 1 to implement the combinational logic gates - inverter and NAND2. We are using the "Misc-Dig" Group and within the Group use the "TIL" Family. Apart from the inverter and NAND2, you will also need a 3x8 decoder (with inverted outputs) and 2 positive-edge triggered Flip-Flops. You can find these two components in the same Group (Misc Dig) and the same Family (TIL). You can use DCD_3to8 for the decoder and D_FF for the Flip-Flop. The D_FF will also come with two additional pins: a SET and a RESET. When SET=1, the output (Q) of the D_FF is set to "1". When RESET=0, the output (Q) is reset to "0". During normal operation both SET and RESET should be set to 0. Only when you are initializing the state-machine to a known state (say, 00), you will use the SET and RESET signals. Connect the input (X) to an input source. You can use the INTERACTIVE_DIGITAL_CONSTANT that we have used in Lab1. Connect the SET signals of both the Flip-Flops together and connect that to an INTERACTIVE_DIGITAL_CONSTANT. Similarly connect the RESET signals of both the Flip-flops together another INTERACTIVE_DIGITAL_CONSTANT. Thus, you can SET and RESET them together as needed. If you need to initialize the FSM to "01" or "10", then you will need to connect the SET and RESET signals of each Flip-flop separately to 2 different INTERACTIVE_DIGITAL_CONSTANT sources. Finally, connect the CLK of the two Flip-flops together and connect to another INTERACTIVE_DIGITAL_CONSTANT. Finally connect PROBEs to all the output nodes (S0 and S1 in this case). 6 Note: If you double click on any components, you will be presented with a menu. Under Label->RefDes you can change the name of the component. This will allow you to keep track of the signals. For example, the INTERACTIVE_DIGITAL_CONSTANT connected to the CLK input should be called CLK. Similarly for SET, RESET etc. Once, you are done, the Multisim schematic should look like this. SET 0. Key = Space So INPUT_X U6 2.5 V 1 U5 U7 SET Key = Space A YO. D . 0 B Y1. C Y2. Y3 NOT Y4. Y5 .RESET Y6. O Y7. b D FF 0 G. DCD_3TO8 S1 U1 C U8 2.5 V SET D NAND2 CLK . ~ Q 6- CLK RESET 0 D_FF Key = Space RESET 0 Key = Space Running the Experiment: Now you are all set to run the experiment. You can see that the simulation is setup in a manner that the CLK is not continuously generated. You will toggle the CLK input manually from 0 to 1 to 0 for every clock cycle. Since we are using positive- edge triggered Flip-flops, you will see changes at the output of the FSM (S0 and S1), when you toggle the CLK from 0 to 1 (i.e., the positive edge). To run the experiment, first RESET the outputs of both the Flip-flops to 0s. This indicates the State A from the State Transition Table. Next, keeping the CLK=0, set the correct input (X). You can set it to either 0 or 1. As a result the FSM to primed for the next state-transition. Next, toggle the CLK from 0 to 1 (at which point you will see the new state updated on S0 and S1), and then from 1 to 0. Now you are ready for the next state transition. Always remember to change the input (X) first keeping the CLK to 0. Then toggle the CLK from 0 to 1 and then finally to 0, to capture the state transition. Following this principle, fill up the Table 1 from the check-off Problem 1 in the next page. 7 Check-off Problem 1: As you run the simulations of the above circuit, observe the outputs (S0 and S1). Correspondingly identify the state of the FSM and fill up the Table below: Table 1: State A Input 0 State Input State Input State Input State Input State Input State Input 1 State 1 0 0 0 TA Initials: Lab (2): Implementing the Pre-lab state machine in Multisim. Now implement the pre-lab state machine in Multisim. Connect the sources and the PROBES to the circuit as required. Check-off Problem 2: As you run the simulations of the above circuit, observe the outputs (S0 and S1). Correspondingly identify the state of the FSM and fill up the Table below: Table 2: State A Input State Input State Input State Input State Input State Input State Input State 1 1 1 0 1 1 TA Initials: 8