ECE2411 Logic Circuits II – Lab #1 Submission Details: For all problems, (1) submit your typed Verilog code (.v) and (2) report file (see exemplary report file on Canvas) with

the waveforms (via screen capture). A Verilog hand-written solution with no simulation will receive no credit. O ABCD O Problem 1 [20 pts] (a) Write a Verilog code of the following combinational network using concurrent statements. Assume that all gate delays are zero. (b) Test your design with the following input combinations and provide waveforms. 1101 ABCD = 1011 2/9/24 ACD A O O O BADB A C Lab Assignment #1 A 0 0 0 1 1 Problem 2 [40 pts] (a) Write Verilog code for a 1-bit full subtractor using logic equations. The truth table for 1-bit full subtractor is shown below. B Bin 0 0 0 1 D 0 0 0 1 1 0 1 1 Diff Bout 0 1 1 0 0 Spring 2024 [Full score: 100 pts] D 1 (b) Test your design with the following input combinations and provide waveforms. A = 0, B = 0, Bin = 1 A = 0, B = 1, Bin = 0 A = 1, B = 0, Bin = 1 A = 1, B = 1, Bin = 0 -Z 1/2 ECE2411 Logic Circuits II - Lab #1 Spring 2024 (c) Write a Verilog code for a 5-bit full subtractor using your 1-bit full subtractor defined in (a). (d) Test your design with the following input combinations and provide waveforms. A = 10001, B = 00011, Bin 0 A = 11001, B = 00111, Bin = 1 O O Problem 3 [40 pts] (a) Write a Verilog code for a simple Arithmetic and Logic Unit (ALU) that implements 8 functions as described in Table 1. Table 1 shows the encoding of the control input. (** Read the design restrictions carefully) (b) Test your design (all for operations) by providing proper inputs and observe outputs on the waveform window. You need to come up with inputs and expected outputs. The 6-bit ALU has the following inputs and outputs: Inputs Control 000 001 010 011 100 101 110 111 2/9/24 = Outputs A: 5-bit input [a positive number; no sign bit] B: 5-bit input [a positive number; no sign bit] Cin: 1-bit input Control: 3-bit control input o Output: 5-bit output O Cout: 1-bit output EQ_check A >>3 A >>>3 Table 1: ALU Instructions Operation Output: A + B + Cin; Cout: a carry Output: A - B - Cin; Cout: a carry Output: A when Cin=0; B when Cin=1 Instruction Add Sub Mux -A (negative A) | Output: ~A + 1 Xor Output: A xor B Output: 0 when A==B; 1 otherwise Output: logical shift right by 3 Output: arithmetic shift right by 3 Design guideline use behavioral method use behavioral method use a case statement use 2's complement use a concatenation operator The following things should be taken care of: Use a case statement that checks the "Control" and acts on A, B, and Cin as described in Table 1. (** case statement should be in 'always' block) ● All the ALU operations are completely combinational. Verilog coding should follow the given design guidelines described in Table 1. 2/2