ELEC/XJEL 3285 Integrated Circuit Design Exercise
Assignment Proforma:
Enter your Student ID in adjacent Box > :
This Lab-book assessment will be worth 10% of the overall module mark and
marked out of 10 i.e. reflects somewhere in the region of 6-12 hours of total study
and reporting effort. The bulk of which is in learning the capabilities of the design tool
in terms of making and simulating the design of logic gate primitives (that a designer
may go on to use in a much more complex multi-gate design) coupled with the
subject understanding.
Please attempt to answer all sections using the word proforma below (to help speed
up the process. Please DO NOT cut and paste as images any of your own textual /
discussion answers, or similar from books or my notes to illustrate your answers.
Obviously, you will need to cut and paste images of any of your simulations, i.e.
graphs, layout pictures or other data, and that's ok. If you cut and paste your own
text as images marks will be deducted, i.e. type in the answers yourself - you can
cut and paste text from your own previous word documents as you have worked
through parts 1 and 2, but just not text as images. Save your final answers in your
own word document and convert to.PDF file for submission via Turnitin.
Do not forget to add your Student ID in the box above.
Later the questions will become quite challenging and require an excellent working
knowledge of the tool which you should be developing here and along the way,
provided you are taking this exercise seriously. To succeed you should be trying to
learn the relationships to the technology and underlying principles, which involve
using the various dialogue and reporting windows to try to extract the information on
the individual transistors from the tool (i.e. variables), and for your specific
technology and transistors used.
If you are really keen and want to go that “extra mile” (not marked but will give you
some invaluable understanding – and I'm more than happy to help in the teams or
private chat area), then try when armed with the variables (which can be found using
the various values the tool uses) to attempt to "close-the-loop" by checking the
Microwind results, with your calculations using the approximate formulae from my
notes and compare with the Level 1 Spice model. The data is all there for you to
attempt this (but if you can't find what you need then try using your best guesses for
the missing variables (comment on this) and carry on) and of course these variables
will be specific to the transistors and technology that each of you have used. You should attempt to answer all the questions yourself, as there is no one correct or
unique answer. It is highly unlikely that any two workers would get exactly the same
behaviour between your models and the simulations.
The important evidence that I am interested to see in your answers. Is your
understanding of how to use the various aspects of the tool, from a basic level (pass)
through to quite an advanced level (top marks). As well as your discussions of what
you observe and then relating this to what you expect from the lectures, and
additional reading and use of the CAD tool - again from a basic level (pass) to higher
levels for top marks.
Key to this is:
1) Getting to know a CMOS transistor: a close-up study of the layout of the
NMOS and PMOS transistors (2-D and 3-D) general construction and
dimensions, and materials used.
2) Being able to simulate and understand the DC, leakage and transient
characteristics of the PMOS and NMOS transistors, and able to report on how
the physical and geometrical variables, i.e. those that you can control and
those that depend on the underlying / chosen technology, contribute to these
electrical characteristics (DC & transient).
3) How the transistor characteristics and gain ratios and channel resistances
(indirectly evidenced) depend on 1) above, and think about how these might
relate to the switching behaviour of an inverter (timing) where they are used
as a complementary pair, with and without additional loading (fanout) on the
output. Just try this with a single transistor for now by adding additional
capacitance to one side of the transistor.
Each response box can be extended into several pages and should include
clear figures and screen-shots and individualised comments (typically no
more than 100-200 words and a few good illustrations should be needed for
each part question), and based on your own understanding and work with the
tools.
Like all assessments, the marks gained tend to be asymptotic in terms of time
spent on the answer. i.e. if you spend 50-100% of the appropriate time
completing the question, and can demonstrate that you understand what you
are doing, then you should be able to get between 60-80% of the total marks.
The remaining 20% involves demonstration of a deeper understanding and
often more time to develop and demonstrate this.
-
Some of the latter questions cover some more complex understanding and
use of the tool – Even then there are simple aspects to those questions – so
do as much of this that you can.
- Q1 (3 Marks)
Use the 2-D and 3-D viewing tools to report on the general construction of the NMOS
and PMOS transistors and any noticeable differences especially for significantly
different technology nodes – I compared 45n with 250nm nodes in my screencast - I
want you to choose different foundries or technology nodes.
Q1 (4 Marks)
Investigate and then discuss how the gate thickness, permittivity, width and length,
along with the other physical variables affect the threshold and channel resistance
and off-leakage for the different transistors (as seen from the DC and transient
characteristics) - This question aims for you to demonstrate your understanding of
these underlying relationships.
For higher marks, discuss how the low leakage, high speed and high voltage
variants as well as the different technologies effect these transistor (IDS versus
VDS/VGS characteristics, and how this capability of the Microwind tool is useful.
Remember to include any relevant screen-shots to support your discussions.
Q2 (3 Marks)
Construct a pass transistor and using a clock signal (just a changing input signal in
this case) and confirm the expected behaviour and weak logic problem, as seen in
the transient characteristics for your PMOS and NMOS transistors with ideally
different threshold voltages.
Try adding additional capacitance to the viewing node – start small say 10fF and not
the effect.
For higher marks include a deeper discussion of how the threshold and technology
choices from your simulations relate to this behaviour, on channel depth and off
leakage - with appropriate evidence.
Remember to include any relevant screen-shots to support your discussions.
