Lab Assignment 1 Part 1 Latches Objectives Use NOR and NAND logic gates to construct and operate S-R latches and D latches. Explain the operation of a basic S-R latch and Gated S-R latch. Explain the operation of a gated D latch ■ Explain the difference between an S-R latch and a D latch. Components ■ Multisim Circuit Simulator ■ 7400N 2 input NAND · 7402N 2 input NOR 7406N Inverter ■ Probe Introduction The latch is a type of temporary storage device that has two stable states (bistable) and is normally placed in a category separate from that of flip-flops. Latches are similar to flip-flops because they are bistable devices that can reside in either of two states using a feedback arrangement, in which the outputs are connected back to the opposite inputs. The main difference between latches and flip-flops is in the method used for changing their state. This experiment will demonstrate how a group of logic gates such as NOR and NAND compose latch circuit and act as a temporary information storage device. Procedure Step 1 Build the SR NOR Latch circuit in Figure 1 using Multisim and verify the operation of the circuit by changing the set and reset inputs. Pay attention to the state of Q and Q outputs while you change input combinations. Fill out the state table of the SR NOR Latch. VCC 5V 25V Reset U1A 7402N Key = Space U2A Set 7402N Key = Space Figure 1 SR NOR Latch S R Q ē 0 0 Qbar 0 1 2.5V 1 0 1 1 Step 2 Build the SR NAND Latch circuit in Figure 2 using Multisim and verify the operation of the circuit by changing the S and Ŕ inputs. Pay attention to the state of Q and Q outputs while you change input combinations. Fill out the state table of the SR NAND Latch. VCC 5V 2.5 V Setbar U1A S R Q Q 7400N Key - Space 0 0 Qbar T 0 1 2.5V 1 0 U2A Resetbar 7400N Key = Space 1 1 Figure 2 SR NAND Latch Step 3 Build the Gated SR NAND Latch circuit in Figure3 using Multisim and verify the operation of the circuit by changing the set, reset, and EN inputs. Pay attention to the state of Q and Ō outputs while you change input combinations. Fill out the state table of the Gated SR NAND Latch. VCC 5V Set 2.5 V U3A U1A S R EN 7400N Key - Space 7400N 0 0 1 EN Qbar 0 1 1 2.5 V Key - Space U2A U4A Reset 7400N 7400N Key = Space 1 0 1 1 1 1 X X 0 Figure 3 Gated SR NAND Latch 0 Step 4 Build the Gated D Latch circuit in Figure 4 using Multisim and verify the operation of the circuit by changing the D and EN inputs. Pay attention to the state of Q and Ō outputs while you change input combinations. Fill out the state table of the Gated D Latch. VCC 5V 2.5 V D U3A U1A D EN Q 7400N Key Space 7400N 0 0 EN Qbar 1 1 2.5 V X 0 Key= Space U2A U4A U5A 7400N 7400N 7406N Figure 4 Gated D Latch Submission: • • • • Save your Multisim simulation file as EET230_Lab#_YourName. Be sure Submit word document file (no zip file) All screenshots of Multisim must capture the date of the simulation. Attach each circuit file of your experiment's simulation separately.