Problem 1. [50 pts] PMOS amplifier with diode connected load An amplifier circuit is shown below. All the capacitors have very large capacitance, and thus can be considered as DC block,

but AC pass-through. VIN Rus 10ΚΩ C1 M2 IBI 10uA VDD 3.2V 182 10uA ↓ VG Beside the parameters on the schematic, given: PMOS: Vt.p = 0.62 V, Hp Cox = 36 UA/V² M1 R₂₁ 100ΚΩ C2 M R₁ 50ΚΩ R₂ 50ΚΩ (W/L)1 = 20 um / 4 um. (W/L)2 = 5 um/ 4 um. The total input voltage VIN has the DC value VIN-2 V and the small sinusoidal signal amplitude Vin=10 mV, i.e. VIN= VIN + Vin- Ignore channel length modulation in calculating in question a, b, and c. Neglect body effect. a. Find the DC voltage at the gate of the transistor, VG. b. Find the DC values of Vov, VS1, VD1, and determine if the transistor in saturation. c. Find the DC voltage at the output, Vo. d. Find the values for transconductance gm for M1 and M2. e. Given the Early voltage |VA| = 10 V, find resistances ro of the two transistors. f. Find the expression and small-signal output resistance Ro. g. Find the expressions and values of small-signal gain vo/vin. h. Calculate the signal amplitude at the output, vo? i. What is the maximum small-signal input voltage amplitude, i.e. maximum input voltage swing, that makes sure the transistors stay in saturation? (Hint: note that in this question, the DC bias voltages for the input and output do not change. However, as the input voltage swing gets larger, the output voltage swing can get too large that pushes the transistor out of saturation.)/nName Problem 2. [30 pts] Simulation Simulate the circuit in Problem 1. • In this simulation, you would need to do the following: o ECE 102 HW4 Body terminal of a transistor should be connected to its Source to avoid body effect. o Set all the capacitors to very large value, for example, 1 F. • In LTspice you should put only "1" in the cap value because F (Farad) is already the default unit of capacitance. If you add "1 F" in the value, LTspice will interpret it as 1 ff which is too small. o For vsig, use a voltage source with AC Amplitude value set to 1. To acquire bias condition, you should perform .op simulation and report ID, VG, VD and VS. o To acquire gain for each stage, you should perform .ac simulation using decade sweep (and not linear sweep) and use the plot Expression to plot VG/Vsig, Vo/VG, and Vo/Vsig. • The frequency sweep in the .ac simulation should be from 1 Hz to 10 GHz. Show the screen-capture of results with highlighted results for the following parameters: a. Include a screen short of the simulated schematic. b. M1: report ID1, VG1, VD1 and Vs1. c. DC voltage at Vout d. Gain: vc/Vsig, Vo/VG, and vo/Vsig. This should be a Bode plot. e. Apply a sinusoidal signal at the input with amplitude of 10 mV and frequency of 1 kHz, full signal plot VG and vo. f. Following e, increase the amplitude until the output voltage is distorted (i.e., the output is not a good sinusoidal waveform anymore). Compare this amplitude value with question (i) in Problem 1 and give a brief comment what happens.