Problem 1Refer to Figure 1, which depicts a Manchester carry chain with one PTL structure per static CMOS "sandwich.” (i) The possible “charging” and “discharging” paths associated with the unit cell have been highlighted inblue/green (charging) and red/black (discharging). In your own words, explain/describe why these are theonly possible "charging" and "discharging" paths associated with the unit cellHint: Based upon our definitions for the P/G/D signals, can multiple signals be active per bit-columnposition? (ii) An engineer is interested to obtain the M=1 version of the unit cell, and suggests that the NMOS and PMOStransistors of the static CMOS inverter need to be sized 6 and 12, respectively. In your own words,explain/describe why this makes senseHint: How do the equivalent worst-case charging/discharging resistances compare to that of a M=1 staticCMOS inverter? (iii) Assuming that Tiny = 38ps and gamma inv = 0.7, estimate the delay associated with the M=1 version of the unitcell