Problem 5. [20 pts] Simulation Simulate the circuit in Problem 3 in HW2 and show the screen-capture results of bias, and gain for VG/Vsig, Vo/VG, and vo/v'sig. R=100KΩ O RGI 3ΜΩ m CIF V sig . RG2 6MQ VDD=3.3V G C3 HD RD ΙΚΩ D Beside the parameters on the schematic, given: S Rs 1.2ΚΩ In this simulation, you would need to do the following: C2 the length of all the transistor L = 4 um. Vt,n=0.48 V, μnCox = 90 UA/V² V₂ Set all the capacitors to very large value, for example, 1 F. R₁ ΙΚΩ In LTspice you should put only "1" in the cap value because F (Farad) is already the default unit of capacitance. If you add "1 F" in the value, LTspice will interpret it as 1 ff which is too small. For Vsig, use a voltage source with AC Amplitude value set to 1.

Fig: 1