PUBLIC/ CYHOEDDUS Marking Max Grade Marks 70-100 Q1 15 22 Q2 15 (1st) 60-69 (2:1) 50-59 (2:2) 40-49 (3rd) 0-39 (Fail) 70-100 (1st) 60-69 (2:1) 50-59 (2:2) 40-49 (3rd) 0-39 (Fail) 70-100 (1st) 60-69 (2:1) 50-59 Q3 20 (2:2) 40-49 (3rd) 0-39 (Fail) Q4 10 Q5 10 70-100 (1st) 60-69 (2:1) 50-59 (2:2) 40-49 (3rd) 0-39 (Fail) 70-100 (1st) 60-69 (2:1) 50-59 (2:2) 40-49 (3rd) 0-39 (Fail) 70-100 Q6 10 (1st) Rationale A perfectly created schematic, using appropriate components, with all necessary parts for bridge rectifier. The different sections of the schematic are clearly identified A well-thought-out schematic, but with some minor faults. A schematic that is readable and contains some good parts, but with some flaws. The simulation is fully running but with some flaws in the results. A poorly organised schematic, where some of the functionalities are not present or that the simulation is not fully running. An incomplete schematic, where the functionalities are not all present, and that simulation is not properly running. The simulation is fully functional and demonstrates that all the requirements are met The simulation is partially functional and demonstrates that some of the requirements are met A simulation is partially functional and contains some good parts, but with some flaws in the results. A poorly organised simulation, where some of the functionalities are not present or running. An incomplete simulation, where the functionalities are not all present or incorrect. A perfectly created layout, using appropriate footprints. Perfect silk position and references. All layers appropriately used and labelled. A very good layout, using appropriate footprints. Good silk position and references. Layers mostly appropriately used and labelled. Overall good layout, using appropriate footprints. Good silk position and references. Layers mostly appropriately used and labelled. Functional layout. Most of the silk there but with room for improvement. Poorly executed layout. Thoroughly worked and well developed chart with inclusion of most relevant process functions and potential failure effects, causes, and controls with RPN. Valid and most effective action results. A well-developed chart with possible potential functions and potential failure effects, causes, and controls with RPN. Valid effective action results. Chart showing potential failure effects, causes, and controls with RPN and effective action results. Attempt to develop a chart with potential failure effects, causes, and controls with RPN and action results. A poor work with process functions and not suitable failure effects, causes, and controls with no/ poor RPN and effective action results. Very concise, informative and clear explanation provided around the arrangements of handling product to be safe from ESD A very good explanation provided around the arrangements of handling product to be safe from ESD A good level of information around the arrangements of handling product to be safe from ESD Satisfactory but incomplete and not highlighting relevant arrangements of handling product to be safe from ESD Poor/ Incorrect/ No arguments, explanations and reasoning of relevant arrangements of handling product to be safe from ESD Comprehensive calculations with all the necessary steps for mean and range calculations with their respective fully labelled charts Q7 and 8 10 (2:2) 40-49 Q9 10 PUBLIC/ CYHOEDDUS 60-69 (2:1) 50-59 (2:2) 40-49 (3rd) 0-39 (Fail) 70-100 (1st) 60-69 (2:1) 50-59 (3rd) 0-39 (Fail) 70-100 (1st) 60-69 (2:1) 50-59 (2:2) 40-49 (3rd) 0-39 (Fail) Correct calculations with all steps well written with respective well labelled charts Calculations with few missing steps with respective well labelled charts Attempt to perform calculations with respective charts not labelled properly A poor work with wrong/no/ or incomplete charts Comprehensive calculations with all the necessary steps well written Correct calculations with all steps well written Calculations with few missing steps Attempt to perform calculations A poor work with totally wrong calculations Comprehensive and well-structured VSM capturing the entire value stream. Well-developed VSM that covers most essential process functions Reasonably well-developed VSM but might be lacking in completeness or clarity. VSM is presented, but it may lack thoroughness in capturing key process functions. The VSM is of poor quality, lacking in the identification of key process functions. Full Wave Bridge Rectifier Circuit with various EMI filters (110 Marks) Full Wave Bridge Rectifier converts AC to DC. EMI in AC-DC conversion begins with conducted currents into the input. Conducted EMI can also appear as common-mode or differential mode noise at various stages during power conversion. Different components are used at each stage in power conversion to reduce conducted EMI. EMI filters can be used to clean up the conducted EMI (noise) throughout a power conversion system. The full bridge rectifier with shunt capacitor filter is shown below. +12V બ CONN-SIL1 ον CONN-SIL1 -12V D1 B C D CONN-SIL1 TR1 1N4007 R1 +88.8 C1 10k Volts 2200u +88.8 AC Volts TRAN-2P3S D2 1N4007 O/P to CONN-SIL1 Component R L C Alternator Diode GND 1 ☑ CONN-SIL1 Transformer Connectors Value / Part Reference 10 K, MINRES10K 68 uH, ELJ-SA680KB 2200 μF, HITEMP2200U25V1090M 325V,50Hz 1N4007 TRAN-2P3S Primary inductance: 180 +12V, OV, O/P and GND, CONN-SIL1 Figure 1. The full bridge rectifier. PUBLIC/ CYHOEDDUS Tasks 1. You are required to create a schematic of a full bridge rectifier on Proteus against above figure and specifications and analyse the output signals without and with EMI filters. The EMI filters which you will use are CL, LC, π and T filters. You will place each filter at the output of bridge and analyse the results. L m L m CL filter L m TT filter L m LC filter C T filter Figure 2. The EMI filters: CL, LC, è and T filters. L m. (15 Marks) 2. Simulate your schematic and compare the results of all the rectifier type and find which filter type is best and why? (15 Marks) 3. Create PCB layouts for each rectifier type considering the requirements from the following specification. a. Keep the trace routing as short and as direct as possible. The shorter the routing, the less potential there is of generating EMI. b. Keep the traces for routing as wide as possible too. The wider the trace, the lower the inductance, which will also help to minimize EMI. c. Route high-current lines at 45 degrees instead of at right angles. Could you investigate and draft why 45 degree is better than 90 degree? d. Develop a 3D of your PCB using 3D visualizer. Bonus marks question: a. In your initial design without any filters, replace the THD rectifier diodes with Surface Mount Device (SMD) rectifier diodes in both the schematic capture and PCB layout. Identify the SMD counterpart for 1N4007. b. Mount SMT rectifier diodes on soldering side and other THD components on component side of pcb. 4. Construct an FMEA for this product. PUBLIC/ CYHOEDDUS (4 x 5 = 20 Marks) Plus 10 bonus marks (20 Marks) 5. Discuss the necessary arrangements for handling this product so it stays safe from ESD. (10 Marks) 6. In a PCB manufacturing industry the excessive heat test is performed to test high temperature capability. Excessive heat can lead to warping in the lengths, widths and thicknesses of different PCB layers and disruption of circuit lines. Excessive heat test is one of the important quality control factor. During testing phase, project team performed the PCB capability study. In Analyse phase collected 20 sets of PCB temperature samples with a subgroup size of 4. Measured values Sample 1 2 3 4 1 44 26 24 34 2 50 48 51 43 3 32 28 26 22 4 52 55 56 44 5 16 16 21 26 6 36 36 35 31 7 21 22 18 21 8 29 21 23 22 9 26 46 44 14 10 24 22 22 44 11 18 24 24 49 12 24 20 26 23 13 19 21 27 28 14 8 11 12 12 15 24 18 27 24 16 56 52 56 50 17 32 22 18 25 18 8 12 11 17 19 51 54 52 49 20 30 28 35 22 Table-Temperature results from 20 PCB samples Calculate the mean (X) and range value (R) for each subgroup and develop the X bar and R charts. From the calculation results and charts, do you think the process is controlled or out-of-control? Ensure the charts are clearly labelled. (10 Marks) 7. In a small PCB manufacturing plant, the total time available is 500 mins. per day and the total quantity of PCBs manufactured, as per costumers demand are 800 units. The total operator cycle time (Step #1 to Step #4) is shown in Table below. How many operators are required to meet the costumers demand? Step #1 Operator Cycle Time = 5 Step #2 Operator Cycle Time = 4 Step #3 Operator Cycle Time = 4 = 7 Step #4 Operator Cycle Time PUBLIC/ CYHOEDDUS Table - Operator cycle time for each step of manufacturing (5 Marks) 8. For the Lean assembly, total operation time is 16 mins, and the customer demand for that period is 24 units. We can see that we have an estimated average inventory level of 12 units before the operation and average inventory level of 10 units after the cycle time (C/T). The cycle time is 8s as shown in figure: xtakt time ?₁ Assembly C/T (SS c/o Batch 1 6 8 s www 2 *takt time Figure 3 - The waiting time and process time • Calculate Takt time? • Calculate the waiting times before and after the 8s cycle time, shown by '?' in figure? (5 Marks) 9. Value Stream Mapping for Power Supply Manufacturing Instructions: In this question, you are tasked with creating a value stream map (VSM) for a power supply manufacturing process. Value stream mapping is a vital tool in Lean and Six Sigma methodologies, helping organizations identify and eliminate waste in their processes. This exercise will give you an opportunity to apply VSM concepts and techniques to a real-world scenario. Scenario: You work for a company that produces power supplies used in various electronic devices. Your task is to map the current state of the manufacturing process for a specific power supply model, known as "PSX-2000." Objective: Your goal is to create a value stream map that illustrates the entire process from raw materials to finished goods for the PSX-2000 power supply. This should help identify areas of improvement and inefficiency within the manufacturing process. Data and Cycle Time Information (for a single unit of PSX-2000): İ. ii. Customer Demand: The customer demand for PSX-2000 is 100 units per day. Cycle Time: The cycle time for each process step is as follows: • Raw Material Inventory: 2 hours • Component Assembly: 1.5 hours • Quality Control and Testing: 0.5 hours • Final Assembly: 1 hour • Packaging: 0.5 hours