Q3. [6 Pts: 1.5, 1.5, 3. pts, 15 minutes] Conceptual questions:

1. Suppose we are building a computer system around a processor\core that is capable of

running at 500 MHz. The processor cycle time is 2ns (nanoseconds). Suppose we can

build a data cache that takes less than 2ns to respond to a read request, so a cache hit

would not slow down the processor at all, and a main memory that takes 100 ns or 50

cycles to similarly respond, forcing the processor to stall for those 50 cycles. We are

considering a range of cache sizes in our design. Suppose we chose a cache size that

would give a cache hit rate of 99%; what is the average memory access time?

Solution:

2. We want to use each thread to calculate two elements of a vector addition. Each thread

block process 2*blockDim.x consecutive elements that form two sections. All threads

in each block will first process a section first, each processing one element. They will

then all move to the next section, each processing one element. Assume that variable i

should be the index for the first element to be processed by a thread. What would be

the expression for mapping the thread/block indices to data index of the first element?

Folution: