The objective of this lab is to design a Differential to a single ended amplifier (See the help document for PSRR and CMRR) Parameters: • Vdd = 2.2V, total current from

supply: IVDD 20 UA. • Ensure that tail current source is implemented with a transistor (no ideal current source in tail). • • Open loop: Load Cap: CL = 1.5 pF. o Gain > 30 dB. o output swing >= 1.6 Vpp. VDD lb VIN+ VOUT LOVIN- DC, AC Analysis (20): Draw small signal model, find Gain and Rout. VING VOUT 000 • Set proper VDSAT, Ib and VICM (input common mode DC) to satisfy the swing and gain requirements of the circuit. Make sure that the drain voltage on all the devices is set properly. • Find W/L, VGs and VDs, and Ips for all the devices. • Calculate the AC parameters gm, ro, etc. . Draw low frequency small signal model (i.e exclude Cgs, Cgd, etc.) - Find Gm, Gain, Rout. Simulations: AC, DC, Gain, Transient and Frequency Response