Verilog

Questions & Answers

2: Construct timing diagram [5 points] Graph the signals that result for the circuit you drew for Step 1 of the prelab. Assume that the propagation delay is much shorter than the step size of 1 second per division. In other words, when an input causes an output transition, you will see it at the same time as the signal that caused the transition. You should also assume that the initial state of the Q output of the flip-flop is 0.


4: Instantiate structural flip-flops in Verilog [10 points] Next, you will simulate a ring counter using Verilog. Let's do so in a manner more similar to how you will construct your lab experiment. In your lab experiment, you will use two 74HC74 dual-D-type flip-flops. Each of these chips contains two flip-flops. Each of those flip-flops has an active-low asynchronous reset (also called "clear") and an active-low asynchronous set (also called "preset"). Although a Verilog simulator can model any kind of logic, the Verilog simulator is strictly limited to disallow anything not supported by the FPGA we use for the class. Our simulator will not allow a flip-flop with both a reset and a set, since it is not supported by our FPGA. Each flip-flop can only have either a reset or a set. We will use the two models provided for the 74HC74 in the course References directory. One of them has an active-low reset 'rn' and the other has an active-low set 'sn'. Each one has 'd', 'c', 'q', and 'qn' lines for the data input, clock input, Q output and inverted output, respectively. You can see the implementation of these modules as well. For this exercise, create a new simulator workspace named "lab7". Rename the default file tab from "template.sv" to "prelab7.sv". Start with the standard top module provided by the simulator. Append the module definitions for hc74_reset and hc74_set below top. In the top module, create an instance of hc74_reset and connect its clock to pb[0], connect its data input to pb[1], and connect its non-inverted output (q) to right[0]. Connect its active-low asynchronous reset (rn) to the 'W' button (pb[16]). Use <shift>-click to press and hold the 'W' button to make sure pb[16] is high. With this, you have a system where the right[0] LED illuminates after a rising edge of the clock (0 button) when the '1' button is held down. If the right[0] is on, it is cleared the instant the 'W' button is released. This is the nature of an active-low reset.


1. Write Behavioral Verilog code (using case statements) for the following sub-modules: a. 4-to-1 multiplexer b. 8-to-1 multiplexer Once you've written both modules, create blocks from the code. In order to write the modules properly for a symbol block, each input and select line must be declared independently. Inside the Verilog module, combine the select lines and inputs into a bus (e.g. a wire with multiple bits). An example of this type design for a 2-to-1 multiplexer is given below.


2. Create a full adder as a logic diagram using only 4-to-1 multiplexers and NAND gates. Use the 4- to-1 multiplexer blocks that you designed in problem #1. Use Cin as select line 1 and X as select line 0.


3. Create a full adder schematic with your block from problem #2 and the input/output pins X,Y, Cin, Cout, S. Perform a waveform drawing showing the outputs for all possible input values. Show the output of your drawing, demonstrating that it works correctly as a full adder.


4. Create the function F(A, B, C, D) = ABC' + C'D' + BCD + A'B'D + AB'D' using an 8-to-1 multiplexer and only NOR gates on the front-end. As select lines, use S₂ = C, S₁ = D, So = A. Use the 8-to-1 multiplexer block you designed in problem #1.


5. Perform a waveform drawing on your circuit from Problem #4 and show the outputs for all possible input values.


Given the input waveforms shown in Fig. 1, sketch the output, Q, of an SR latch.


Q7


Q8


You have to submit: • Truth table input from 0000 to 1111. • K-map • Verilog Code. • Waveform


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