4: Instantiate structural flip-flops in Verilog [10 points]
Next, you will simulate a ring counter using Verilog. Let's do so in a manner more similar to how you will
construct your lab experiment. In your lab experiment, you will use two 74HC74 dual-D-type flip-flops.
Each of these chips contains two flip-flops. Each of those flip-flops has an active-low asynchronous reset
(also called "clear") and an active-low asynchronous set (also called "preset").
Although a Verilog simulator can model any kind of logic, the Verilog simulator is strictly limited to
disallow anything not supported by the FPGA we use for the class. Our simulator will not allow a flip-flop
with both a reset and a set, since it is not supported by our FPGA. Each flip-flop can only have either a
reset or a set.
We will use the two models provided for the 74HC74 in the course References directory. One of them has
an active-low reset 'rn' and the other has an active-low set 'sn'. Each one has 'd', 'c', 'q', and 'qn' lines for
the data input, clock input, Q output and inverted output, respectively. You can see the implementation of
these modules as well.
For this exercise, create a new simulator workspace named "lab7". Rename the default file tab from
"template.sv" to "prelab7.sv". Start with the standard top module provided by the simulator. Append the
module definitions for hc74_reset and hc74_set below top.
In the top module, create an instance of hc74_reset and connect its clock to pb[0], connect its data input
to pb[1], and connect its non-inverted output (q) to right[0]. Connect its active-low asynchronous reset (rn)
to the 'W' button (pb[16]). Use
With this, you have a system where the right[0] LED illuminates after a rising edge of the clock (0 button)
when the '1' button is held down. If the right[0] is on, it is cleared the instant the 'W' button is released.
This is the nature of an active-low reset.
