1. Write Behavioral Verilog code (using case statements) for the following sub-modules:

2: Construct timing diagram [5 points] Graph the signals that result for the circuit you drew for Step 1 of the prelab. Assume that the propagation delay is much shorter than the step size of 1 second per division. In other words, when an input causes an output transition, you will see it at the same time as the signal that caused the transition. You should also assume that the initial state of the Q output of the flip-flop is 0.

1. Write Behavioral Verilog code (using case statements) for the following sub-modules: a. 4-to-1 multiplexer b. 8-to-1 multiplexer Once you've written both modules, create blocks from the code. In order to write the modules properly for a symbol block, each input and select line must be declared independently. Inside the Verilog module, combine the select lines and inputs into a bus (e.g. a wire with multiple bits). An example of this type design for a 2-to-1 multiplexer is given below.

4: Instantiate structural flip-flops in Verilog [10 points] Next, you will simulate a ring counter using Verilog. Let's do so in a manner more similar to how you will construct your lab experiment. In your lab experiment, you will use two 74HC74 dual-D-type flip-flops. Each of these chips contains two flip-flops. Each of those flip-flops has an active-low asynchronous reset (also called "clear") and an active-low asynchronous set (also called "preset"). Although a Verilog simulator can model any kind of logic, the Verilog simulator is strictly limited to disallow anything not supported by the FPGA we use for the class. Our simulator will not allow a flip-flop with both a reset and a set, since it is not supported by our FPGA. Each flip-flop can only have either a reset or a set. We will use the two models provided for the 74HC74 in the course References directory. One of them has an active-low reset 'rn' and the other has an active-low set 'sn'. Each one has 'd', 'c', 'q', and 'qn' lines for the data input, clock input, Q output and inverted output, respectively. You can see the implementation of these modules as well. For this exercise, create a new simulator workspace named "lab7". Rename the default file tab from "template.sv" to "prelab7.sv". Start with the standard top module provided by the simulator. Append the module definitions for hc74_reset and hc74_set below top. In the top module, create an instance of hc74_reset and connect its clock to pb[0], connect its data input to pb[1], and connect its non-inverted output (q) to right[0]. Connect its active-low asynchronous reset (rn) to the 'W' button (pb[16]). Use <shift>-click to press and hold the 'W' button to make sure pb[16] is high. With this, you have a system where the right[0] LED illuminates after a rising edge of the clock (0 button) when the '1' button is held down. If the right[0] is on, it is cleared the instant the 'W' button is released. This is the nature of an active-low reset.

Part III Instead of creating a memory module by using the BASIC FUNCTION etc., we can implement the required memory by specifying its structure in System Verilog code. In a System Verilog-specified design it is possible to define the memory as a multidimensional array. A 32 x 4 array, which has 32 words with 4 bits per word, can be declared by the statement logic [3:0] memory_array [31:0]; In the FPGAs, such an array can be implemented either by using the flip-flops that each logic element contains or, more efficiently, by using the built-in memory blocks. 13/nPerform the following steps: Create a new Quartus project. 2. Write a System Verilog file that provides the necessary functionality, including the ability to load the RAM and read its contents as was done in task 2. 1. 3. Assign the pins on the FPGA to connect to the switches and the 7-segment displays. Compile the circuit and download it into the DE1_SOC. 5. Test the functionality of your design by applying some inputs and observing the output. Demo your results by direct presentation to instructor. 4./nPart IV The RAM block in Figurela has a single port that provides the address for both read and write operations. For this task you will create a different type of memory module, in which there is one port for supplying the address for a read operation, and a separate port that gives the address for a write operation. Perform the following steps. 1. Create a new Quartus project for your circuit. To generate the desired memory module open the IP Catalog and select the RAM: 2-PORT module in the Basic Functions On Chip Memory category. Choose "With one read port and one write port" in the category called "How will you be using the dual port ram?" a. Configure the memory size, clocking method, and registered ports the same way as in intro above. Go to Output above./n

USB Power On/Off ELEC 2531 Lab 5 Part 1: Connect to the Board. Step 1: Let us start with understanding the board: BAND Connections, Pins and Seven Segment Lab (3 Parts) ISSI JUES 888888 terasic U 1-SOC Kam ALIO Download DE1-5oC CD from http://cd-del-soc.terasic.com Jogo 0:0 333 wwwww www Board ID/n

Cardinal Network Interface Component Architecture Specification This document specifies the structure and operation of the Cardinal network interface component, which is to be used as a building block of a 4-core chip multiprocessor for the course project for the 2023 Fall EE577B class. Overview The Network Interface Component (NIC) to be implemented to provide a path from the processor to the underlying ring network is a two-register interface, which is simple yet efficient. On the sender side, packets are sent via a single network output channel buffer in the NIC, to which the outgoing packets are written. On the receiver side, packets are received via a single network input channel buffer in the NIC, from which the incoming packets are read. The network input and output channel buffers as well as their status registers are memory address mapped. Thus, processors can access them using regular store/load instructions. As a result, the NIC provides the processors with an interface very much the same as the memory interface so that the processors need not to deal with the details in the network (e.g., handshaking signaling and polarity, among others). The illustration of the processor-network interface is illustrated in Figure 1. Processor Element Net out University of Southern California ExternalInterface Descriptions Net in Network Interface Component Network Processor Element Net out Net in Figure 1: Illustration of the Two-register Network Interface. Refer to Figure 2 and Table 1 for the external signals for the NIC and their respective description. The NIC is a clocked (synchronous) device. The reset is synchronous and asserted high. There are two channels in the NIC: the network output channel and the network input channel. On the network output channel, packets go from the processor to the router. The 64-bit packets from the processor (same packet format as depicted in Part 1 Figure 2) to the router are injected into the din port and delivered to the routers via the net do port. On the network input channel, packets go from the router to the processor. The 64-bit packets from the router are injected into the net di port and delivered to the processor via the d_out port./nOn the other hand, the interface between the processor and the NIC is very similar to the memory interface between the processor and data memory. The 2-bit address specifies one of the internal registers (network input channel buffer, network input channel status register, network output channel buffer and network output channel status register) to be accessed. Table 2 lists the mapping between the address and the registers. Not all the registers can be written by the processors. The network input channel status register, the network output channel status register, and the network Input channel buffer are read-only to the processor. The network output channel buffer is write-only by the processor (there is no need for a processor to read from a network output channel). Unsupported (or illegal) operations to these registers will be ignored by the NIC. The load/store operation to the NIC is synchronized with the clock signal. If nicEn and nicWrEN are both high and addr[0:1] specifies the network output channel buffer, the packet on the din port is written to the output channel buffer at the next rising clock edge. If nicEn is high and nicWrEN is low, the content of the register specified by addr[0:1] is placed onto the d_out port at the next rising clock edge. Because the status registers are 1-bit wide, a valid load from the status register will have the 1-bit register content being placed on the least significant bit of the NIC's data output port (i.e., d_out[63] in Figure 2). All the other bits of the data output port (i.e., d_out(0:62]) should be 0. processor nicEnWr addr[0:1] d_in[0:63] d_out[0:63] Signal Name addr[0:1] d_in[0:63] d_out[0:63] nicEn net si nicEn nicWrEn Signal Туре Input Input status reg 2 Input 64 Output 64 Input 1 Input 1 1 buffer network output channel network input channel Figure 2: cardinal_nic Module External Interface. Table 1: Signal Description for Cardinal NIC Bit Width clk reset buffer status reg net so net ro net_do[0:63], net_polarity net sl net ri net_di[0:63] Description router Specify the memory address mapped registers in the NIC. Input packet from the PE to be injected into the network. Content of the register specified by addr[1:0). Enable signal to the NIC. If not asserted, d_out port assumes 64'h0000_0000. Write enable signal to the NIC. If asserted along with nicen, the data on the d_in port is written into the network output channel Send handshaking signal for the network input channel. When asserted, indicates channel data is a valid packet that should be latched at next rising clk edge into the internal channel buffer. 3/nnet ri net_di[0:63] net so net ro net_do[0:63] net_polarity cik reset Output 1 Input Output Input Output Input Input Input 64 1 2'b01 2b10 2b11 1 64 1 1 1 addr[0:1] 2'600 Ready handshaking signal for the network input channel. Asserted when the network input channel buffer is empty. Packet data for the network input channel. Send handshaking signal for the network output channel. Asserted when the channel buffer has packet to send and net ro signal is asserted. Ready handshaking signal for the network output channel. When asserted, indicates the router has space for a new packet. Packet data for the network output channel. Polarity input from the router connected to the NIC. Clock signal. Reset signal. Reset is synchronous and asserted high. Table 2: NIC Register Address. NIC internal registers Input channel buffer Input channel status register Output channel buffer Output channel status register InternalRegisters A typical NIC design implements two First-In-First-Out queues to store packets from processor to the network and from network to processor, respectively. In the Cardinal NIC design, the two FIFO queues are simplified as two 64-bit registers. One register is for the network output channel, thereby being called network output channel buffer. Another register is for the network input channel, thereby being called network input channel buffer. Consequently, the NIC can store and forward one packet at a time for each of the two directions. Besides the channel buffers, each channel has a 1-bit status register to track whether the channel buffer is empty or not. When the channel buffer is full, the corresponding channel status register is set to high. When the channel buffer is empty, the corresponding channel status register is set to low. After a reset, both channel status registers are reset to 0. Handshakingwiththe Router The handshaking between the Cardinal NIC and the Cardinal Router is similar to that between two Cardinal Routers. For the network input channel, the channel control asserts the net_ri signal to indicate that this NIC has available buffer space for a new packet from the router that is connected to this NIC. The net_ri signal can then simply be regarded as an indication of whether the corresponding buffer is occupied or not. When the router has data that it wishes to forward to the processor and if the net_ri signal of the corresponding NIC is asserted, the router asserts its pe so signal along with placing the packet on the data channel. At the NIC side, when the net si input signal is asserted, the data on the channel should be clocked into the channel buffer on the next rising clock edge. On the other hand, for the network output channel, the NIC checks the net ro and net polarity input signals when it has a packet in the channel buffer to be injected into the network. If net ro is asserted and net_polarity indicates that the right router virtual channel is accepting packets, the NIC asserts the net so output signal and places the packet data on the network output channel. In the case of blocking that happens when the router is not ready for a new packet, the packet stays in the NIC's output channel buffer. 4/nFurthermore, no more packets from the processor are accepted. Figure 3 gives the handshaking signals on the network output channel. In the actual implementation, the NIC will only inject packets into the network during either even or odd polarity to avoid network deadlock. After system reset, the net so signal should be negated (reset to 0) and the net_ri signals should be asserted (set to 1). ♫ CLK RESET net polarity net_ro net_do net so Even InterfacingwithProcessor Figure 3: Sample Handshaking Timing Diagram at Network Output Channel. Odd The processor uses regular load and store instructions to access the internal registers of the NIC. The load and store instructions are defined in the "Cardinal Processor ISA Manual" in part 2 of this project. One memory reference instruction can either access the NIC register or access data memory. But it cannot access both at the same cycle. Processor should be able to distinguish the operation based on the immediate address field of the load/store instruction, as the channel buffers and status registers of the NIC are mapped to the processor's address space. The address mapping adheres to the following rule. For the 32-bit memory address output from the cpu, memAddr[0:31] in a memory reference instruction (load/store instruction), If memAddr[16] and memAddr [17] are both 1, the address refers to a NIC register. The least significant 2 bits (memAddr [30:31]) specify the NIC register according to Table 2. If memAddr [16] and memAddr [17] are not both 1, the address refers to a data block in the data memory, where only the least significant 8 bits are used for our data memory simulation model, just as before. This is a regular memory reference. You will need to alter your Part 2 Cardinal Processor design to ensure that the memEn signal is asserted correctly for this case. You will also need to make alterations to the design to add output signals for nicEn and nicEnWr. Finally, you will also need to alter the processor design for loads to multiplex between the data out from the data memory and NIC appropriately depending on which device is being accessed. The processor design will have two input ports for data from the data memory and for data from the NIC, respectively. 5

Assignment 1 [40 points]: Design a 4-bit Ripple Carry Adder that adds two 4-bit inputs and produces a 4-bit Sum and 1-bit Carry Out outputs. a) Use VHDL for behavioral coding (code for zero delay - no input to output delays). [5] b) Write a testbench with the following inputs to test out (a) above: 1010+ 0101 1100 + 0111 0101 + 0101 Demo results on Vivado. [5] c) Use VHDL for structural coding with basic gates to design Half-Adder and Full Adder structurally, and then use these intermediate components to structurally build up to the 4-bit Adder. All basic gates will have 1ns internal delays. [20] d) Using the testbench of (b), test out (c) above. Demo results on Vivado. [10]

Objective • 8-bit signed adder • X, Y (1 bit sign, 7 bit value) • Multiple operations X (+0) X + 1 X-1 (0) - X Binary input • Decimal Output (0) - Y X + Y X - Y Y-X

Synchronous Counters Upon completion of this lab, you should be able to • Design Synchronous Counters with a MOD Number <2N. Equipment Lab Objectives 1. Quartus Prime 2. Altera DEO-CV Development Board (Figure 1) 3. USB Cable Allocated Time: 2 hours DEP-CV Crotone) Lab 6

Frequency Division and Asynchronous Counters Upon completion of this lab, you should be able to 1. Use JK flip flops to design basic count up/down systems. Equipment Lab Objectives 1. Quartus Prime 2. Altera DEO-CV Development Board (Figure 1) 3. USB cable Allocated Time: 2 hours muff 88AAG DEO-CV Con terasic RA wwwwwwwww Cene K