1. Write Behavioral Verilog code (using case statements) for the following sub-modules: a. 4-to-1 multiplexer b. 8-to-1 multiplexer Once you've written both modules, create blocks from the code. In order to

write the modules properly for a symbol block, each input and select line must be declared independently. Inside the Verilog module, combine the select lines and inputs into a bus (e.g. a wire with multiple bits). An example of this type design for a 2-to-1 multiplexer is given below.