Tasks to be completed The ultimate goal of this lab is to implement a 4-bit adder using structural VHDL. To achieve this goal, create a new folder, name it, for example,

lab 3, and follow the steps below. 1. Using the data flow approach, write the VHDL code to implement a half adder. The schematic of a half adder is illustrated in figure 8. Compile and simulate your design. Create a VHDL component from the current file (refer to the procedure in the introductory example). Make sure to log your results - Screenshots of both the VHDL code and simulation. A A B B S B Figure & Half Adder 2. Using the structural approach, write the VHDL code to implement a full adder. The schematic of a full adder is illustrated in figure 9. Make sure to declare all the necessary components, including the OR2 gate. Compile and simulate your design. As you did in 1), create a VHDL component from the current file. Make sure to log your results - Screenshots of both the VHDL code and simulation. Halfadder с C Halfadder S Figure 9: Full Adder using two half adders -Sum 3. Using the full adder component defined in 2) and structural VHDL, write the code to implement a 4-bit adder. A 4-bit adder has already been implemented in Lab 2 using schematic. Compile your design, assign pins as necessary and programme the DEO-CV board (same pin assignments as in Lab 2). Test your design to check its functionality by using the onboard switches and LEDs - refer to the pin assignments of Lab 2. Copy a screenshot of your VHDL code to your logbook and get your lab tutor to check your implementation. END of LAB 3