UNIVERSITY O F LIVERPOOL Department of Electrical Engineering and Electronics ELEC143 Coursework Design of a two-stage inverter chain Module Coursework name Component weight Semester HE Level Lab location ELEC143 Design of a two-stage inverter chain 20% 2 4 N/A Work Timetabled time Suggested private study Assessment method Submission format Submission deadline Late submission Resit opportunity Marking policy Anonymous marking Feedback Subject of relevance Learning outcomes Individual 0 hours 24 hours (preparation and report writing) Individual, formal word-processed report Online via Canvas (anonymous) Standard University penalty applies August resit period via resit exams Marked and moderated independently Yes via Canvas Inverter designs and layouts, MOSFET models (LO5) Familiarity of common design rules for development of layouts for silicon devices and simple circuits. (S2) - Experience and enhancement of following discipline: specific practical skills: designing & debugging digital circuits; handling & measurement of components. (S3) - Demonstrate ability in applying knowledge to: design combination logic circuits with up to 4 inputs; analyse and to design simple sequential logic circuits; an ability to design a simple MOS circuit including tolerance and feature sizes. (S4) - Knowledge of basic design methods for combinational and sequential logic circuits; understanding of number systems; knowledge of the laws of Boolean algebra; understanding of how physical laws of semiconductor apply to practical diodes & transistors; appreciation of why certain materials are used in devices; familiarity with common designs of devices, and simple MOS circuits. - 1- Marking Criteria Section Marks available Report 10% presentation and structure Introduction, Method and Calculations 30% Device and 45% circuit layouts Discussions and Conclusion 15% Indicative characteristics Adequate / pass (40%) • Contains cover page information, table of contents, sections with appropriate headings. • Comprehensible language; punctuation, grammar and spelling accurate. • Equations legible, numbered and presented correctly. • Appropriately formatted reference list. Very good / Excellent (> 40%) • Word-processed with consistent formatting. • All sections clearly signposted. • · Pages numbered, and figures and tables captioned appropriately. Appropriate use of technical, mathematic and academic terminology and principles. • Correct cross-referencing (of figures, tables, equations) and citations. • • Appropriate use of references and format. Appendix containing any additional evidence i.e. further results, graphs, photographs etc. • Problem background introduced clearly and objectives correctly presented. • Appropriate methodology used in calculating the aspect ratio of all devices. • Justification of any assumptions made. • Aspect ratio of all devices correctly presented in terms of minimum feature size. • Individual device layouts are correctly presented. • Different regions within respective layout is easily distinguishable. • Appropriate scale is defined. • Results from each layout is accompanied by appropriate commentary. • Basic discussion demonstrating an understanding of the underlying concepts. • Conclusions correctly inferred from the calculation, results and layouts. • Evidence of wider reading. • Evidence of basic reflection and self-criticism. • All calculations shown in full. • All devices are correctly calculated. • Summary table of the calculated aspect ratio presented in terms of minimum feature size. • Design decisions are justified using at least one external source. • Further justification and explanation of any assumptions made. • All device layouts are correctly the presented in terms minimum feature size. • Appropriate alignment accuracy is included within respective layouts. • Overall circuit layout is correctly presented, i.e. correct connections, including interconnects and contact pads. • Minimal area is utilised in the circuit layout arrangement. • Thorough analysis is presented, including justification on the selection of aspect ratios and area minimisation. • Meaningful reflection on the limitations work, and insight into possible realistic improvements. -2- 1. Overview The aim of this coursework is to design a two- stage inverter circuit, shown in Figure 1. Initially, this involves calculating respective dimensions of the different devices in the circuit (i.e. MOSFETs A, B, and C, and passive load resistor RL) using appropriate models / equations, and parameters / constants provided Vin below. Following on this, respective layouts for each of the devices, and an overall circuit, including interconnects and contact pads, needs to be generated accurately, on scaled or graph RL Vo' Figure 1 Vout wwww VDD paper/s with stipulated scale (e.g. 1 µm = 1 cm). Accurate alignment error between layouts must also be included with minimal area utilised. All of the dimensions/areas of the layouts need to be expressed in terms of the minimum feature size (2m). 2. Description: The circuit in Figure 1 consists of 2-stage inverters (two NOT gates), with respective input, Vin and output, Vout. The 1st stage of the inverter consists of an enhancement n-MOST A (driver) and a saturated n-MOST C (load), whilst the 2nd stage consists of an enhancement n-MOST B (driver) with a passive load RL. In terms of operation, the logic at the output follows the logic at the input after some delay, i.e. if Vin is at logic 1, then Vout is logic 1 and vice versa. This circuit forms part of a ring oscillator, which typically comprises of odd number of inverters, connected in a loop as discussed in ELEC143. The output oscillates between two logic levels, and used to determine gate delays or operation speeds of circuits. However, for this coursework, the main objective is to understand and implement approaches in generating and representing circuit layouts appropriately with effective use of area as discussed in ELEC143. 3. Useful hints Focus on the first-stage inverter (i.e. driver A and load C) and determine the respective aspect ratios (W/L) of these transistors. Assume the input into A is at logic 1 (i.e. driver A is on), then the intermediate output Vo' is at logic 0. This output logic is fed into the input of the second inverter i.e. driver B. You will need to select an appropriate value for this - 3- intermediate output voltage Vo' corresponding to a logic 0. Note this needs to be lower than the threshold voltage of the driver B so as to ensure that B remains off at logic 0 input. Furthermore, load C is always on and operates in saturation. Refer to ELEC143 lecture notes on the MOSFET/inverters. The on-resistances of the drivers A and B can be assumed to be the same. Similarly, the on-resistance of load C can be assumed to be equal to that of the passive load RL. However, the dimension of C is not the same as RL since these are different devices. Refer to ELEC143 notes on p-n junction (passive load). The layouts must consider the alignment accuracy (2a), which can be assumed to be equal to the minimum feature size λm or multiple of 2m. 4. Parameter/constants Below are respective values for use in the calculation: i. Minimum feature size, λm = 0.5 μm ii. Supply voltage, VDD = 5 V (logic 1 input) iii. Threshold voltage of the transistors, VT = 0.3 V iv. Sheet resistance for the load resistor, Rsheet = 100 Q2/square V. Device constant is given as below: W W B = (μCo) = (Bo) — L L Note: The mobility μ and gate capacitance Co can be assumed to be the same for all transistors, i.e. ßo = 1.8 × 10-4 AV-2. 5. Report Individual report should include ALL of your calculations and justify any assumption made. The report must also include individual design layouts of all the devices and an overall design layout of the circuit in Figure 1, including interconnects and contact pads on scaled graph papers. The layouts must be expressed in terms of the minimum feature size with appropriate alignment errors. Different shading could be used to differentiate regions of the respective layouts. The area of the overall layout needs to be effectively utilised. The deadline for the submission of the report is Wednesday 8th May 2023 by 23:59 on Canvas. - 4-