Design a 64*64 Sram array block. Each array block has 8 WL. I need total four such blocks. The arrangement should be such that the control block should be in the

middle of the 4 blocks. Control block contains pre-decoder, decoder. The final output should be of 128 bits. Please provide diagram with all the above details along with peripheral circuits such as write drivers, pre charger circuits, sense amplifiers, output latches and FF, column mux and any other parts necessary. Please provide the individual sizes and configurations of each circuit block used.