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Q1:1. Preliminary calculations for max current We will be building an AC to DC converter with our diode. Of course this will not be perfect, and there will be a so-called "ripple voltage": the peak-to-peak voltage of the wobble in the voltage waveform left over from conversion. Your task is to help me select a diode while balancing power and cost limitations. Let us introduce a 12 V amplitude AC signal at a frequency of 60 Hz-imagine we set a 14:1 transformer to take power from the wall outlet (120 V... @ 60 Hz). Also, assume the load resistance is 1 kOhm. What is, ignoring the diode forward bias voltages for now, the expected current going through the load and thus the diodes themselves? Treat this as a ballpark value for the next steps.See Answer
Q2:Initial choice of diode and I-V characteristic sanity check For now, choose a diode that can handle the repitive forwardSee Answer
Q3:Peak circuit output current and output voltage Now would be a good time to check if our Ballpark estimate from (1)See Answer
Q4:Bridge rectifier output Let us now simulate the bridge rectifer circuit, shown below.See Answer
Q5:5. Secondary choice of diode through cost considerations Look up your chosen diode on www.digikey.com. Suppose we make one bulk purchase and make all the bridge rectifiers we can out of it. How many circuits can we build, and how much do the diodes cost? Are there any cheaper alternatives that would still work? Provide cost estimates from the Digikey website. Digikey screenshots are needed here.See Answer
Q6:6. Turning the output signal into a DC signal Provide some method of turning your output waveform from (4) into a DC signal. If not perfectly DC, then at least an oscillating signal, not necessarily sinusoidal, that has a ripple voltage of 99-101 mV. Assume all the same parameters: 12 V amplitude, 60 Hz, 1 kOhm load. Hint: RC decay. Simulate your new full circuit in LTSPICE and estimate the additional cost, assuming we want to finish the same total number of circuits as in (5). SPICE plots and Digikey screenshots are needed here.See Answer
Q7:Instruction: Use any circuit simulation tool to answer the problems below. 1. A BJT differential amplifier is biased from a 2-mA constant-current source and includes a 100-2 resistor in each emitter. The collectors are connected to +10 V via 5 k resistors. A differential input signal of 0.1 V is applied between the two bases. Assume that the transistors are matched and have ß-100 and Is=14 fA. (a) With the aid of LTSpice (or any other circuit simulation tool), determine the signal current in the emitters i, and the base-emitter voltage vibe for each BJT. (b) What is the total emitter current in each BJT? (c) What is the signal voltage at each collector? (d) What is the voltage gain realized when the output is taken between the two collectors? R₁ = 5 ΚΩ Q₁ +5 V -5 V 2 mA Q2 02 R₂ = 5 ΚΩ Vi Ri Vcc = +10 V 150 150 Ω 0.5 mA 20 ΚΩSee Answer
Q8:Noninverting Amplifier (a) 2. The circuit for this step is the noninverting amplifier shown in Figure 12-11. Using the measured resistances from step 1, compute the closed-loop gain of the noninverting amplifier. The closed-loop gain equation is given in the text as Equation 12-8. Enter the computed value in Table 12-10. (e) (f) V₁= 500 mV 1.0 kHz Application Activity PROVE PERME (b) (c) Calculate your using the computed closed-loop gain. Record in Table 12-10. Change the circuit to the noninverting amplifier circuit shown in Figure 12- 11. Set the input for a 500 mVpp sine wave at 1.0 kHz with no dc offset. Record the measured setting in Table 12-10. (d) Measure the output voltage, Vor Record the measured value in Table 12-10. Measure the feedback voltage at pin 2. Record the measured value. Notice that the voltage at pin 2 is not near ground potential this time. Place a 1.0 M2 test resistor in series with the input from the generator. Observe the output voltage with the series resistor in place. You can think of the voltage change as being dropped across the test resistor, the rest is across the input resistance. You can use this to indirectly find the input resistance. Record the measured input resistance in Table 12-10. Table 12-10 +15 V HE 110μF 741C 44 10μ -15 V Figure 12-11 www 116 R₁ 10 k R₁ 1.0 kn Parameter Vin ACKNI) Vout Ve Rin Computed Measured Value Value 500 mVppSee Answer
Q9:To complete the initial introduction to Elvis sections (parts A, B &C) of the lab no pre-laboratory exercise is required. Please complete the following pre-laboratory exercises. 1. (3pts) For the circuit shown in Fig. 2, derive the transfer function for Vo/Vin in terms of R, C and find the expressions for the magnitude and phase responses. Express your results in the form Vo Vin Vin(t) jw Wp jw Wp Where wpid the pole frequency location in rad/sec 1+ C He R Vo(t) Fig. 2. First order high pass filter (integrator) 2. (3pts) For C= 10nF, find R so that pole frequency location is 4.8 kHz. Draw the bode (magnitude and phase) plots using MATLAB, Python or Excel. 3. (4pts) Simulate the high pass filter circuit using the PSpice simulator (Capture CIS 17.4 ). Compare the simulation results with your hand-calculation. Attach the magnitude and phase simulation results and compare them with part 2 results (bode plots).See Answer
Q10:To complete the initial introduction to Elvis sections (parts A, B &C) of the lab no pre-laboratory exercise is required. Please complete the following pre-laboratory exercises. 1. (3pts) For the circuit shown in Fig. 2, derive the transfer function for Vo/Vin in terms of R, C and find the expressions for the magnitude and phase responses. Express your results in the form Vo Vin Vin(t) jw Wp jw Wp Where wpid the pole frequency location in rad/sec 1+ C He R Vo(t) Fig. 2. First order high pass filter (integrator) 2. (3pts) For C= 10nF, find R so that pole frequency location is 4.8 kHz. Draw the bode (magnitude and phase) plots using MATLAB, Python or Excel. 3. (4pts) Simulate the high pass filter circuit using the PSpice simulator (Capture CIS 17.4 ). Compare the simulation results with your hand-calculation. Attach the magnitude and phase simulation results and compare them with part 2 results (bode plots).See Answer
Q11:To complete the initial introduction to Elvis sections (parts A, B &C) of the lab no pre-laboratory exercise is required. Please complete the following pre-laboratory exercises. 1. (3pts) For the circuit shown in Fig. 2, derive the transfer function for Vo/Vin in terms of R, C and find the expressions for the magnitude and phase responses. Express your results in the form Vo Vin Vin(t) jw Wp jw Wp Where wpid the pole frequency location in rad/sec 1+ C He R Vo(t) Fig. 2. First order high pass filter (integrator) 2. (3pts) For C= 10nF, find R so that pole frequency location is 4.8 kHz. Draw the bode (magnitude and phase) plots using MATLAB, Python or Excel. 3. (4pts) Simulate the high pass filter circuit using the PSpice simulator (Capture CIS 17.4 ). Compare the simulation results with your hand-calculation. Attach the magnitude and phase simulation results and compare them with part 2 results (bode plots).See Answer
Q12:Pre-laboratory exercise 1. (2pts) For the summing amplifier in Fig. 1 with power supplies +7V, choose R2 to have Vout= -(Vini +2Vin2), if R1 R3 = 10KN. 2. (2pts) Use CIS Capture/Pspice to verify your hand-calculation and confirm that the circuit operates as a summing amplifier. For Vin1 use a VSIN source with the following settings (VOFF-0, VAMPL=1, FREQ=1kHz, AC=1). For Vin2 use VDC source with a value of 2Vdc. Run a Time Domain (Transient) simulation profile for 2ms. 3. (2pts) For the differential amplifier in Fig. 2 with power supplies +7V, choose R1 to have Vout= (Vin2 - Vint), if R2 R3 R4 = 10K 4. (2pts) Use CIS Capture/Pspice to verify your hand-calculations and confirm that the circuit in Fig.2 operates as a differential amplifier. For Vin1 use a VSIN source with the following settings (VOFF-0, VAMPL=1, FREQ=1kHz, AC-1). For Vin2 use VDC source with a value of 2Vdc. Run a Time Domain (Transient) simulation profile for 2ms. 5. (2pts) Use OrCAD Capture /Pspice to check the common-mode gain and CMRR for the circuit in Fig.2. For Vinl use a VSIN source with the following settings (VOFF-0, VAMPL=1, FREQ=1kHz, AC-1). For Vin2 use VDC source with a value of 1Vdc. Run a Time Domain (Transient) simulation profile for 2ms. Use the cursors to find the common-mode gain and differential-mode gain then calculate CMRR.See Answer
Q13:Task 1: Three-phase half-wave diode rectifier with R load Recall Chapter 1, Make a new project. Build a three-phase half-wave diode rectifier with R load. Use the sinusoidal source in the SOURCE lib set amplitude 110V and frequency 60Hz. Use the diode and load parts in the PSpice Component set resistor 5.2. Use the time domain simulation set up, set run to time as 50ms and maximum step size as le¹³. a. Show your analysis tab of simulation settings. b. Plot the load current. c. If we want to simulate an open circuit error happening at source phase a (0 deg shift) for this rectifier, 1) Show your modified schematic for this new simulation. 2) Plot the load current again. 3) Compare your answer for part c.2) with part b, briefly explain your plots.See Answer
Q14:Task 2: Single-phase half-wave phase-controlled rectifier with RL load Recall Chapter 2, Make a new project. Build a single-phase half-wave phase-controlled rectifier with RL load Use the sinusoidal source in the SOURCE lib set amplitude 450V and frequency 20Hz Use the pulse voltage source in the PSpice Component and set the rising time lus, falling time /us, pulse width 100μs, low-side output voltage OV, and high-side output voltage 201 Use the load parts in the PSpice Component set resistor 50, and inductor 20mH in series. Use the thyristor in the ELEC4174_Fall_2023 library. Use the time domain simulation set up, set run to time as 50ms and maximum step size as le a. Show your schematic. b. If we have voltage pulse (gate signal) appears at 15ms, 1) Plot the voltage across the resistor and voltage across the inductor. 2) Find the conduction angle (approximately) using results in part b.1). 3) Evaluate your plots in part b.1) for maximum value for VR and the point when V₁ across 0, briefly explain with words or equations what happened there.See Answer
Q15:1) Generate the Ip vs Vps plots within the power supply limits of 0-3V, do this for gate- source voltages between zero and 3V spaced by 0.5 volts for both our default NFET and our PFET (W/L-5/0.5). This covers the full operating range of our devices. Label each trace with the VGs voltage used for each curve. For the NFET your plot should look qualitatively like this: 104 VGSI-VTH Saturation Region HLA-ESDA HLA-ESDA Vass Vosz Vast To do this you need to use a DC parameterized sweep with two loops, in one loop you are sweeping VDs and the other you are stepping VGs. To get the PFET characteristic to look like this you will need to change the signs of the some of the voltages and currents. b) Plots of the simulation results Repeat for the PFET Vos Careful: getting the PFET scans is trickier than you think, be sure that you cover the triode and saturation regions. (need the screenshots for these) Questions: For the NFET a) A legible copy of your simulation schematic, make sure it shows the device length and width a) For similar absolute values of the bias voltages the PFET and NFET drain currents are different, why? b) Observe how the slope of the curves in saturation change for different Vos. What does this imply about ro, the small signal output resistance as a function of Ves? c) What would the maximum current be if instead of a 5 micron wide device you had a 20 micron wide device?See Answer
Q16:2) Next generate a plot for Ip vs Vos for the diode connected NFET over 0-3 V of VDS bias. Include on your plot the effect of a bulk voltage of -0.5, 0, 0.5 and 1V. The easiest way to get all 3 curves on the same plot is to use 3 instances of the device in your simulation schematic, each with different bulk bias voltages. Using NET aliases can be useful here. Repeat for our PFET but now with bulk bias voltages of 3.5, 3, 2.5 and 2V. Here you should clearly see the body effect on the transistor characteristic. Replot these for the square root of ID vs VGs and estimate the effective threshold for each bulk voltage. For the NFET a) Schematic used for the simulation b) Plot showing the simulation results for ID vs VGs for the different bulk voltages. c) Plot of the square root of ID vs VGS for the different bulk voltages. d) A table showing the threshold voltages vs the bulk bias Then include the same for the PFET. (need the screenshots for these) General observations and suggestions: be sure you have a proper ground or the simulator will not work, it needs to be set as node zero. Setting the bias will be a challenge for many of you. Think about the meaning of the sign of the current. To make the PFET plots look "normal" you can change the signs of the voltages and currents plotted as appropriate. Use enough points in your simulation to make the curves look smooth. Note: clearly label the axes, label the traces with the Vgs or bulk bias voltages used, also make the traces thicker than the default and adjust colors for readability. Be careful in your choice of NFET3 or NFET4, only use the 3 terminal version if you are sure that the source voltage will always be at ground for the NFET. The NFET3 and PFET3 versions have their source and bulk terminals tied together internally. For our process this cannot be done for the NFET but it can for the PFET.See Answer
Q17:6. In part 5, Provide LTspice simulation for all three parts of the above experiment. Compare the experimental and simulation results. This part hasSee Answer
Q18: Project 2 Assignment Computer Simulation of Transient Voltages 1 Abstract- This document describes the second of two computer-based projects assigned to students. In this project the software packages LTspice and Matlab are used. Part A of the project deals with lumped parameter circuits and Part B deals with distributed parameter transmission line circuits. Part C describes briefly the written report. Appendixes have been written to clarify details. Associated with this assignment is a rubric that should be consulted. Part A - Lumped Parameter Circuits Preface to Part A - For Part A several circuits will be simulated with an array of parameters. Objectives are to 1) explore under damped, over damped and critically damped series and parallel RLC circuits and 2) explore transient recover voltage (TRV) circuits. Procedures for Part A SERIES RLC CIRCUITS The series RLC circuits being simulated are described in Figure 1 and Table 1. L ros t=0 Vo T C '2₁ (+) m Figure 1. Series RLC circuit. Circuit Name "Over" "Under" "Critical" Vo(V) 7.32 x 10³ 7.32 x 10³ 7.32 x 10³ Table 1. Parameters for three different series RLC circuits. C(F) 7.32 x 10-6 7.32 x 10-6 7.32 x 10-6 Undamped Natural + Frequency: 1 fo= 27/LC (Hz) 2+√LC 7.32 x 10³ 7.32 x 10³ x 10³ V₂ PARALLEL RLC CIRCUITS The parallel RLC circuits being simulated are described in Figure 2 and Table 2. vi (t) t=0 L = 1 (2πfo)²C (H) Use LTspice to simulate the three series RLC circuits with the parameters shown in Table 1. Use your undergraduate text to obtain the analytical expressions for the current i₁(t) that you expect to flow in the three series RLC circuits named "over", "under" and "critical". export your LTspice data for i₁(t) to Matlab and compare the LTspice results with the analytical equations. Plot the Matlab-generated results from your equations as a solid line and plot the LTspice results as data points (show a legend on your Matlab plot so that the reader is clear about how you are presenting LTspice data compared to data generated from your analytical expressions.) Students should obtain quite good agreement (say 3% or better) between LTspice and the analytical equations. Save Matlab and LTspice plots and screen captures for your report (Part C). Include in your report Table 1 containing numerical values for all of your parameters. -To Calculate Calculate Calculate Calculate Calculate Calculate w Figure 2. Parallel RLC circuit. Characteristic Impedance: Zo = √√12 R R(Q) 5(2Z0) (2Zo)/5 (2Zo) Circuit Name "Over" "Under" "Critical" Vo(V) 7.32 x 10³ 7.32 x 10³ 7.32 x 10³ Table 2. Parameters for three different parallel RLC circuits. Undamped Natural C(F) 7.32 x 10-6 7.32x 10-6 7.32 x 10-6 Frequency: 1 fo = 2mLdHz) 2π√LC R 7.32 x 10³ 7.32 x 10³ 7.32 x 10³ roos L •Vmain (wt) с L = 1 (2πfo)²C (H) vi Calculate Calculate Calculate Use LTspice to simulate the three parallel RLC circuits with the parameters shown in Table 2. For this part there will be no detailed comparison to theory thus there is no requirement that you use Matlab. Capture for your report (Part C) LTspice plots of v₁(t) for the circuits in Table 2 named "Over", "Under" and "Critical". Include in your report Table 2 containing numerical values for all of your parameters. TRANSIENT RECOVERY VOLTAGE (TRV) CIRCUITS The TRV circuits being simulated are described in Figure 3 and Table3. t=t₂ Joon Characteristic Impedance: Zo = √√/2 Figure 3. TRV circuit. Calculate Calculate Calculate 5₁ R Ω (Zo/2)/5 5(Zo/2) (Zo/2) Circuit Name "Large X/R" "Small X/R" Table 3. Parameters for two different TRV circuits. See the three notes below the table. Vm(V) 7.32 x 10³ 7.32 x 10³ @ (rad/sec) 2π60 2+60 C(F) [Note 1] 7.32 x 10-⁹ 7.32 x 10-⁹ L(H) 7.32 10 X 3 7.32 x 10-3 TRV Undamped Natural Frequency: 1 fo=27(Hz) Calculate Calculate X R || 5 @ L R 15 5 R(Q) Calculate t₁ (s) [Note 2] Calculate [Note 2] t₂ (s) [Note 3] [Note 3] Note 1: When S₁ closes at t = t₁, the energy stored in C will discharge into the shorted path consisting of S₁ and S₂ in series with C, resulting in very large high frequency oscillations if the "loop" inductance is not handled properly. The instructor solved this (high current at high frequency) issue by inserting series resistance and series inductance into the model for C. See Figure 4 for an example of how the instructor modeled C in LTspice. Note 2: Use t₁ values that give symmetrical fault current (no DC offset current). Establish t₁ via trial-and-error or best via phasor analysis. Note 3: Use t₂ values that provide switch opening at the current zero closest to one 60-Hz period after the fault is applied. When a breaker clears at a non-current-zero time then the phenomenon is called "current chopping" and we are not studying that presently thus it is important to have t₂ equal to the time at which the natural current zero appears. Establish t₂ via trial-and-error or best via phasor analysis (making t₂ equal to "t₁ plus the 60-Hz period" is the correct approach, assuming that your t accurately gave a symmetrical fault current.) Use LTspice to simulate the two circuits with the parameters shown in Table 3. For this part there will be no detailed comparison to theory thus there is no requirement that you use Matlab. For the two sets of circuit parameters in Table 3, capture for your report (Part C) LTspice plots of 1) generator voltage; 2) switch S₁ current; 3) TRV voltage v₁(t); and 4) an expanded time scale showing the current as it approaches extinction and a few cycles of the TRV voltage (as the instructor shows below in Figure 8.) Include in your report Table 3 containing numerical values for all of your parameters. Describe in your report how you established t₁ and t₂./nAbstract- This document describes the second of two computer-based projects assigned to students. In this project the software packages LTspice and Matlab are used. Part A of the project deals with lumped parameter circuits and Part B deals with distributed parameter transmission line circuits. Part C describes briefly the written report. Appendixes have been written to clarify details. Associated with this assignment is a rubric that should be consulted.See Answer
Q19:(d) At time t = 0, the capacitor C in Fig. 1(d) is charged to Vc = +1V and the switch S is open. The switch is closed at time t = 100 μs, connecting the voltage source Vs to the RC network. Calculate the voltage on the capacitor at time t = 200 μs: Vs = (3000 + a) mV, R = (2200+B) 02, and C = (100 + y) nF. S R Vc(200μs) Vs SPICE circuit schematic SPICE output C + Vc Figure 1(d) 20% 5% 5%/n(C) Calculate the magnitudes and phases of the phasor representations of the following quantities: e (i) (ii) where f = (1000 + 3) kHz, Is = (100+ a) μA, Vs = (2500 + 5) mV, R = (1800 + E) Q2, L= (2200 +λ) μH, C = (470+ n) pF, (iii) (1) (ii) (iii) (iv) (iv) i₁(t) = 1,cos(wt +0.5) v₂(t) = Vssin(wt - 1.2) Z3 (w) = R + jwL R Z4(w) = Magnitude (with units) 1+ jwCR Phase (degrees) Phase (radians) 30%/nQuestion 1 (60 marks) (a) The combination of resistors capacitors C1, C2, C3 and C4 in Fig. 1(a) is equivalent to a single capacitor Ceq. Calculate the value of Ceg when C1 = (1000 + a) nF, C2 = (2000+ B) nF, C3 = (3000 + y) nF and C4 = (4000 + ō) nF. C1 C2 Ceg www. C4 C3 Figure 1(a) Ceq 15%See Answer
Q20:(d) At time t = 0, the capacitor C in Fig. 1(d) is charged to Vc = +1V and the switch S is open. The switch is closed at time t = 100 μs, connecting the voltage source Vs to the RC network. Calculate the voltage on the capacitor at time t = 200 μs: Vs = (3000 + a) mV, R = (2200+B) 02, and C = (100 + y) nF. S R Vc(200μs) Vs SPICE circuit schematic SPICE output C + Vc Figure 1(d) 20% 5% 5%/n(C) Calculate the magnitudes and phases of the phasor representations of the following quantities: e (i) (ii) where f = (1000 + 3) kHz, Is = (100+ a) μA, Vs = (2500 + 5) mV, R = (1800 + E) Q2, L= (2200 +λ) μH, C = (470+ n) pF, (iii) (1) (ii) (iii) (iv) (iv) i₁(t) = 1,cos(wt +0.5) v₂(t) = Vssin(wt - 1.2) Z3 (w) = R + jwL R Z4(w) = Magnitude (with units) 1+ jwCR Phase (degrees) Phase (radians) 30%/nQuestion 1 (60 marks) (a) The combination of resistors capacitors C1, C2, C3 and C4 in Fig. 1(a) is equivalent to a single capacitor Ceq. Calculate the value of Ceg when C1 = (1000 + a) nF, C2 = (2000+ B) nF, C3 = (3000 + y) nF and C4 = (4000 + ō) nF. C1 C2 Ceg www. C4 C3 Figure 1(a) Ceq 15%See Answer

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