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Q1:5. Secondary choice of diode through cost considerations Look up your chosen diode on www.digikey.com. Suppose we make one bulk purchase and make all the bridge rectifiers we can out of it. How many circuits can we build, and how much do the diodes cost? Are there any cheaper alternatives that would still work? Provide cost estimates from the Digikey website. Digikey screenshots are needed here.See Answer
Q2:Noninverting Amplifier (a) 2. The circuit for this step is the noninverting amplifier shown in Figure 12-11. Using the measured resistances from step 1, compute the closed-loop gain of the noninverting amplifier. The closed-loop gain equation is given in the text as Equation 12-8. Enter the computed value in Table 12-10. (e) (f) V₁= 500 mV 1.0 kHz Application Activity PROVE PERME (b) (c) Calculate your using the computed closed-loop gain. Record in Table 12-10. Change the circuit to the noninverting amplifier circuit shown in Figure 12- 11. Set the input for a 500 mVpp sine wave at 1.0 kHz with no dc offset. Record the measured setting in Table 12-10. (d) Measure the output voltage, Vor Record the measured value in Table 12-10. Measure the feedback voltage at pin 2. Record the measured value. Notice that the voltage at pin 2 is not near ground potential this time. Place a 1.0 M2 test resistor in series with the input from the generator. Observe the output voltage with the series resistor in place. You can think of the voltage change as being dropped across the test resistor, the rest is across the input resistance. You can use this to indirectly find the input resistance. Record the measured input resistance in Table 12-10. Table 12-10 +15 V HE 110μF 741C 44 10μ -15 V Figure 12-11 www 116 R₁ 10 k R₁ 1.0 kn Parameter Vin ACKNI) Vout Ve Rin Computed Measured Value Value 500 mVppSee Answer
Q3:To complete the initial introduction to Elvis sections (parts A, B &C) of the lab no pre-laboratory exercise is required. Please complete the following pre-laboratory exercises. 1. (3pts) For the circuit shown in Fig. 2, derive the transfer function for Vo/Vin in terms of R, C and find the expressions for the magnitude and phase responses. Express your results in the form Vo Vin Vin(t) jw Wp jw Wp Where wpid the pole frequency location in rad/sec 1+ C He R Vo(t) Fig. 2. First order high pass filter (integrator) 2. (3pts) For C= 10nF, find R so that pole frequency location is 4.8 kHz. Draw the bode (magnitude and phase) plots using MATLAB, Python or Excel. 3. (4pts) Simulate the high pass filter circuit using the PSpice simulator (Capture CIS 17.4 ). Compare the simulation results with your hand-calculation. Attach the magnitude and phase simulation results and compare them with part 2 results (bode plots).See Answer
Q4:To complete the initial introduction to Elvis sections (parts A, B &C) of the lab no pre-laboratory exercise is required. Please complete the following pre-laboratory exercises. 1. (3pts) For the circuit shown in Fig. 2, derive the transfer function for Vo/Vin in terms of R, C and find the expressions for the magnitude and phase responses. Express your results in the form Vo Vin Vin(t) jw Wp jw Wp Where wpid the pole frequency location in rad/sec 1+ C He R Vo(t) Fig. 2. First order high pass filter (integrator) 2. (3pts) For C= 10nF, find R so that pole frequency location is 4.8 kHz. Draw the bode (magnitude and phase) plots using MATLAB, Python or Excel. 3. (4pts) Simulate the high pass filter circuit using the PSpice simulator (Capture CIS 17.4 ). Compare the simulation results with your hand-calculation. Attach the magnitude and phase simulation results and compare them with part 2 results (bode plots).See Answer
Q5:Pre-laboratory exercise 1. (2pts) For the summing amplifier in Fig. 1 with power supplies +7V, choose R2 to have Vout= -(Vini +2Vin2), if R1 R3 = 10KN. 2. (2pts) Use CIS Capture/Pspice to verify your hand-calculation and confirm that the circuit operates as a summing amplifier. For Vin1 use a VSIN source with the following settings (VOFF-0, VAMPL=1, FREQ=1kHz, AC=1). For Vin2 use VDC source with a value of 2Vdc. Run a Time Domain (Transient) simulation profile for 2ms. 3. (2pts) For the differential amplifier in Fig. 2 with power supplies +7V, choose R1 to have Vout= (Vin2 - Vint), if R2 R3 R4 = 10K 4. (2pts) Use CIS Capture/Pspice to verify your hand-calculations and confirm that the circuit in Fig.2 operates as a differential amplifier. For Vin1 use a VSIN source with the following settings (VOFF-0, VAMPL=1, FREQ=1kHz, AC-1). For Vin2 use VDC source with a value of 2Vdc. Run a Time Domain (Transient) simulation profile for 2ms. 5. (2pts) Use OrCAD Capture /Pspice to check the common-mode gain and CMRR for the circuit in Fig.2. For Vinl use a VSIN source with the following settings (VOFF-0, VAMPL=1, FREQ=1kHz, AC-1). For Vin2 use VDC source with a value of 1Vdc. Run a Time Domain (Transient) simulation profile for 2ms. Use the cursors to find the common-mode gain and differential-mode gain then calculate CMRR.See Answer
Q6:Task 1: Three-phase half-wave diode rectifier with R load Recall Chapter 1, Make a new project. Build a three-phase half-wave diode rectifier with R load. Use the sinusoidal source in the SOURCE lib set amplitude 110V and frequency 60Hz. Use the diode and load parts in the PSpice Component set resistor 5.2. Use the time domain simulation set up, set run to time as 50ms and maximum step size as le¹³. a. Show your analysis tab of simulation settings. b. Plot the load current. c. If we want to simulate an open circuit error happening at source phase a (0 deg shift) for this rectifier, 1) Show your modified schematic for this new simulation. 2) Plot the load current again. 3) Compare your answer for part c.2) with part b, briefly explain your plots.See Answer
Q7:Task 2: Single-phase half-wave phase-controlled rectifier with RL load Recall Chapter 2, Make a new project. Build a single-phase half-wave phase-controlled rectifier with RL load Use the sinusoidal source in the SOURCE lib set amplitude 450V and frequency 20Hz Use the pulse voltage source in the PSpice Component and set the rising time lus, falling time /us, pulse width 100μs, low-side output voltage OV, and high-side output voltage 201 Use the load parts in the PSpice Component set resistor 50, and inductor 20mH in series. Use the thyristor in the ELEC4174_Fall_2023 library. Use the time domain simulation set up, set run to time as 50ms and maximum step size as le a. Show your schematic. b. If we have voltage pulse (gate signal) appears at 15ms, 1) Plot the voltage across the resistor and voltage across the inductor. 2) Find the conduction angle (approximately) using results in part b.1). 3) Evaluate your plots in part b.1) for maximum value for VR and the point when V₁ across 0, briefly explain with words or equations what happened there.See Answer
Q8:1) Generate the Ip vs Vps plots within the power supply limits of 0-3V, do this for gate- source voltages between zero and 3V spaced by 0.5 volts for both our default NFET and our PFET (W/L-5/0.5). This covers the full operating range of our devices. Label each trace with the VGs voltage used for each curve. For the NFET your plot should look qualitatively like this: 104 VGSI-VTH Saturation Region HLA-ESDA HLA-ESDA Vass Vosz Vast To do this you need to use a DC parameterized sweep with two loops, in one loop you are sweeping VDs and the other you are stepping VGs. To get the PFET characteristic to look like this you will need to change the signs of the some of the voltages and currents. b) Plots of the simulation results Repeat for the PFET Vos Careful: getting the PFET scans is trickier than you think, be sure that you cover the triode and saturation regions. (need the screenshots for these) Questions: For the NFET a) A legible copy of your simulation schematic, make sure it shows the device length and width a) For similar absolute values of the bias voltages the PFET and NFET drain currents are different, why? b) Observe how the slope of the curves in saturation change for different Vos. What does this imply about ro, the small signal output resistance as a function of Ves? c) What would the maximum current be if instead of a 5 micron wide device you had a 20 micron wide device?See Answer
Q9:2) Next generate a plot for Ip vs Vos for the diode connected NFET over 0-3 V of VDS bias. Include on your plot the effect of a bulk voltage of -0.5, 0, 0.5 and 1V. The easiest way to get all 3 curves on the same plot is to use 3 instances of the device in your simulation schematic, each with different bulk bias voltages. Using NET aliases can be useful here. Repeat for our PFET but now with bulk bias voltages of 3.5, 3, 2.5 and 2V. Here you should clearly see the body effect on the transistor characteristic. Replot these for the square root of ID vs VGs and estimate the effective threshold for each bulk voltage. For the NFET a) Schematic used for the simulation b) Plot showing the simulation results for ID vs VGs for the different bulk voltages. c) Plot of the square root of ID vs VGS for the different bulk voltages. d) A table showing the threshold voltages vs the bulk bias Then include the same for the PFET. (need the screenshots for these) General observations and suggestions: be sure you have a proper ground or the simulator will not work, it needs to be set as node zero. Setting the bias will be a challenge for many of you. Think about the meaning of the sign of the current. To make the PFET plots look "normal" you can change the signs of the voltages and currents plotted as appropriate. Use enough points in your simulation to make the curves look smooth. Note: clearly label the axes, label the traces with the Vgs or bulk bias voltages used, also make the traces thicker than the default and adjust colors for readability. Be careful in your choice of NFET3 or NFET4, only use the 3 terminal version if you are sure that the source voltage will always be at ground for the NFET. The NFET3 and PFET3 versions have their source and bulk terminals tied together internally. For our process this cannot be done for the NFET but it can for the PFET.See Answer
Q10:6. In part 5, Provide LTspice simulation for all three parts of the above experiment. Compare the experimental and simulation results. This part hasSee Answer
Q11:1. Design an op-amp circuit that will take a voltage as an input and will amplify it with a gain of A. The input voltage source must be named V3. The named net for the input voltage should be Vin and named net for the output voltage must be Vout. [10 marks]See Answer
Q12:3. Design an op-amp circuit that will take a voltage as an input and will amplify it with a gain of C. The magnitude of the current that flows through the feedback resistor must be between 0.1 mA and 1 mA when the output from the amplifier is the maximum voltage possible (for your power supply voltages). The input voltage source must be named V3. The named net for the input voltage should be Vin and named net for the output voltage must be Vout. The feedback resistor must be named Rf. [20 marks]See Answer
Q13:4. Design a circuit that takes 3 voltages as inputs (a, b, and c) which has an output that is equal to D(Ea-Fb) + Gc. The three voltages sources used for the input voltages should be named VA, VB and VC and they should be connected to your circuit via named nets, named Va, Vb and Vc. [20 marks]See Answer
Q14:[20 mi 5. Create a voltage source labelled V3 and connect the positive terminal to a named net cal... Vin. Set a source resistance for the voltage source by right clicking on it and entering a value into the Series Resistance box. Voltage Source - V3 DC value[V]: Series Resistance[2]: 2000 X OK Cancel Advanced Comment Figure 1: Setting the Series Resistance of V3 (for example to 2000 ohms). The value you use should be between 1000 and 10000 ohms. This setting will give the voltage source an output resistance. Looking from the point of view of an amplifer with an input of Vin, this is the also the source resistance. Design a circuit that will amplify the signal Vin with a gain of H dB. The gain of the circuit must not depend upon the value of Series Resistance chosen above. That is, if the Series Resistance is changed, the value of the output voltage should remain the same or almost identical./nThe named net for the input voltage should be Vin and named net for the output voltage must be Vout. Only use integer (whole number) values of Ohms for your resistances (round the value you require to 0 decimal places). [20 marks]See Answer
Q15:6. Design a circuit where the output voltage will be the difference between two input voltages, connected by named nets Va and Vb (the sources to be named VA and VB respectively), multiplied by J. The output, Vout, should be J (Vb - Va). The output should also be independent of the source resistances of the inputs (see Figure 1 for setting source resistances). It is also a requirement that the gain of the circuit be adjustable using only one resistor, which must be labelled Rg. The named net for the output voltage must be Vout. The common mode rejection ratio (CMRR) must be infinite. [20 marks]See Answer
Q16:Adjusting Transistor Length, Editing Models & Finding Small Signal Parameters. Unfortunately, when you change W and L in the PSPICE MOSFET Level 1 Model (the one we are using) it adjusts some but not all of the spice parameters in the correct manner. Changing W First and easiest to deal with is the area of the source and drain regions. The picture below shows a view of a MOSFET from above. AS is the area of the source and AD is the area of the drain in meters. In the PSPICE model AS and AD remain at their default value as the width is changed, which is incorrect. To fix this I revised the Capture Part to explicitly show AD and AS on the schematic. The areas given for the default 5 micron wide FETs now can be manually changed as you scale the width. For us Ldiff (E in the textbook) will be taken to be 1.5x10 meters (1.5 um) and to remain constant for all transistors. The areas will then be given by AS = AD=1.5x10 x W m². When changing transistor widths, you will need to compute these areas and enter them on the schematic to be passed to the SPICE model. These areas will not be affected by changing L. The good news is that these areas mainly influence the source-bulk and drain-bulk capacitances, they have no effect on currents. So unless you are doing a transient simulation, a frequency sweep or any in which these capacitances matter your answers will still be correct, but I would get in the habit of changing them anyway just so as not to forget, but you don't need to fiddle with them when you are trying to find the DC gain or set up bias conditions. NRS-N(source) PS= 2 x L (source) + W Lag (source) → AS-WXL (source) NRD=N(drain) PD=2x Lag (drain) + W Lag (drain) AD=WxLag (drain)/nThe situation is worse for adjustments to L, the good news is that often you will want to use the minimum length transistor as for the most part these give the best performance; highest speed, best gm for a given drain current etc. However sometimes like for current sources or cascoding transistors among other applications you would like to have transistors with a higher output resistance, ro. You can obtain a higher ro by increasing L. The problem here is that the built-in PSPICE MOSFET model we are using does not change the model parameter LAMBDA as it should. For these 0.5 um long device models Lambda is fixed at 0.1 irrespective of the gate length. It should scale like: where for the NFETs C=0.034 and for the PFETs C=0.064. Lambda=- с с Leff L-2LD These values for C are used so that we get the correct value of LAMBDA for the 0.5 μm long devices. Once you have the correct value of LAMBDA to use with the length that you have chosen you then need to edit the SPICE model for those devices which have the longer length. The next section will describe how to edit the SPICE model for individual transistors in your design. Note: If you want to change the ro of a transistor but not mess with its ID or VGs you can increase W by the same factor that you increased L. That keeps the W/L ratio constant and the ID current equation mostly unchanged. There is another wrinkle about which you should be aware. In saturation we use the formular, 1 AID 1+2 Vps. So, there will MID The MOSFET model equations implemented in PSPICE user= be a small disagreement for devices with a high VDs between hand calculations and SPICE unless you use the same formula that SPICE uses for your hand calculation. Model Editor The model editor is useful for more that just getting the effect of length changes correct. For instance, I used it to set GAMMA to zero in order to turn off the body effect for one of the homework solutions. To open the model editor select the transistor whose model you wish to change. Once selected, it changes color, then right click on the transistor. One of the options that show up in the context menu is "Edit PSPICE Model". Clicking on that opens the model editor. In the text box with the model parameters change the parameters that you wish to adjust. If you choose save then the model is saved in your local design library located in PSpice Resources>Model Libraries in your project Hierarchy on the first page of your project./nI change the model for every transistor that uses that original model in your design. To change the model for only the selected transistor you need to give it a new name. To do this change the name in the text box in the model editor before saving. Here is an example. The original model statement; .MODEL NFET4 NMOS would be edited for example to .MODEL NFET4-L10u NMOS. Now when saved the new model is still saved to your local design library but will apply to only the transistor that you originally clicked on and show up in the left panel of the Model editor with the new name. To use it elsewhere you can then just copy and paste the transistor on your schematic. This sometimes will not update the model name that appears on your schematic. To check which model a FET uses you can select and right click on a transistor and choose "Edit Properties". The Model name that will be used in the simulation is listed in the properties table next to "Implementation". This is all rather poorly documented in the PSPICE help files and manual so I hope that this is clear. Operating Point Here we will look at the effect of length changes on the output resistance of our NFET. Perform a bias point analysis for NFETs with gate lengths of 0,5, 1 and 2 microns. For the L=0.5 µm transistor use a width of 5 μm. Choose the widths of the other transistors so that all 3 transistors have the same W/L ratio. Bias their gates with 200 mV of overdrive and set the drain voltages to 3V. In the Simulation Settings be sure to check the "Include detailed bias point information for nonlinear controlled sources and semiconductors (OP)" option. This will save the small signal model for each transistor to the output file. Once the simulation runs view the Output file in the probe window. Toward the end you will see the list of your transistors and the small signal model parameters at the bias point for each. Copy this table into your report. It also lists the SPICE model parameters for each transistor, this is not what I want to see. Calculate the ro of each transistor to see the effect of the length change. I say calculate because SPICE does not report r, directly, rather it gives you the conductance between drain and source, GDS. In general, the bias point analysis is a good way to see what the small signal parameters are, especially for the parasitic capacitances which can be a bit tedious to calculate. It/non the schematic if you select the appropriate option buttons in the Capture toolbar. This analysis is most useful for setting up your desired bias points for designs. Sweep analysis of ro. Next for the same 3 transistors perform a DC Sweep analysis to generate the Ip vs VDS graph for each transistor. For ease of comparison graph them all on the same plot. Indicate the operating regions on your graph, any transition voltages and label each plot line with the transistor's gate length. Question: The VGs and W/L ratio is the same (or should be) for each transistor why do the curves look different? Explain. The slope of this graph at each point corresponds to the small signal drain-source conductance. Come up with a trace expression that will display to as a function of VDD. Plot ro for each transistor, all on the same plot. Note in particular what happens to ro when the devices enter triode. Often a graph like this will give you a better idea of what is going on than just looking at equations. Provide the equations for ro in each operating region and explain how they relate to your plot. Is your plot reasonable does it qualitatively agree with your plots? This last bit is sort of a check on your simulation, you always need to ask yourself if the SPICE results are reasonable, it is easy to make simulation errors. Provide: Source files PSICE Orcad 16.6 Simulation schematic for Bias point Operating Point Table Calculated Output resistances Simulation schematic for ID vs VDS plot, if different from that above. ID VS VDS Plot Question response To VS VDS plot. ro equations and comparisonSee Answer
Q17: EEEE1004- Coursework #2 Simulation and design of Op-Amp circuits using LTspice In this coursework you will design and simulate some of the op-amp circuits that have been covered in the module (EEEE1004). The set of designs each student will make will be different as all students will receive different design parameters. The design parameters are referred to in this document as letters of the alphabet, and are highlighted, for example A. The value of A can be found from the spreadsheet provided on Moodle, which has a set of values for each student ID. This coursework forms 15% of the mark for the EEEE1004 module. Submission Your coursework submission will consist of a single PDF file (it suggested that this is created using Microsoft Word), containing your working for each of the questions. The individual .asc files (which contain your circuits) that you have created while doing your coursework must also be submitted. These files will be marked by automation of the simulation process and must be named in the following format, with the question number that it relates to, for example, 'Question 1.asc'. Ensure that you label the nets as described in the question. Failure to do so will limit how many marks you will receive. How will this work be marked As part of the automation of the simulation used for marking, different input voltages and currents will be set and voltages and currents around the circuit will be checked to ensure they match those expected from the input parameters given in the task. Full marks will be given to for a task if the simulation meets the requirements given in the question, this includes using the labels and device names described in the text. If the simulation does not meet the requirements, then partial marks are available. The working presented in your report is worth 50% of the marks, with the simulation aspect being worth the other 50%. As mentioned above, the simulation files will be marked by automating the simulation process. Any deviation from using the labels and device numbering required will require manual intervention and the loss of one mark per intervention required (down to 50% of the question mark - ie down to 0% for the simulation aspect of the question). If you show clear and correct working as part of your submission, but fail to submit a working simulation file, the marks will be limited to 50% of the marks available for that question. Partial marks will also be given for your working up to 50% of the marks available for that question. If the simulation presented matches your working, but your working is incorrect, the maximum mark available for the simulation part of the question will not be greater than the marks obtained from the working. If an incorrect amplifier type is demonstrated a mark of zero will be awarded for that question. You should assume that any value of resistance is available and must not limit yourself to using Standard Resistor Values. It is anticipated that you will check that the simulated circuit you have produced meets the design requirements given in the question, that is you can check your own work meets the design requirements before submission through simulation. Note: You are simulating a real op-amp (rather than an ideal one) and therefore the output values will not be exactly what you expect but will very close to the expected output - within 0.02%. Do not try to adjust your resistor values away from the theoretically correct values to get a perfect result. Hints Sometimes hints/reminders are given on how to achieve a task using LTspice, for example labelling a net. The keyboard shortcut will be shown like so, F4, meaning the F4 key on the keyboard should be pressed. How to achieve the same task using the menu bar may also be given, for example "Edit→Label Net", means click on 'Edit' on the menu bar followed by 'Label Net'. Tasks For each task, show your working in your document. You do not need to use an equation editor or similar, so long as the mathematics presented is clear and easy to follow. Suitably cropped photos/scans of handwritten equations inserted into the document are acceptable. When an op-amp is required, only use the LT1097 Op-Amp (this can be found as a component in the 'Opamps' folder in the 'Select Component Symbol' window, found using F2 or “Edit⇒Component”) for this coursework. Unless specified, for each task, the circuit needs to be powered appropriately, you should assume that the output voltages will never be outside the range of ±10V. More than one op-amp might be required to complete some tasks. These must all be powered by named nets from the same pair of power supplies. For all circuits the positive power supply voltages should be named V1 and the negative supply named V2. They should be connected to the correct pins on the op-amps via named nets, named V+ (for the positive supply) and V- (for the negative supply). 1. Design an op-amp circuit that will take a voltage as an input and will amplify it with a gain of A. The input voltage source must be named V3. The named net for the input voltage should be Vin and named net for the output voltage must be Vout. [10 marks] 2. Design an op-amp circuit that will take a current as an input and will amplify it with a gain of B Q. You will need to add a current source to the circuit to demonstrate it working. The conventional current should flow towards ground from the current source. The current source should be labelled I1. The net for the output voltage must be labelled Vout. [10 marks] 3. Design an op-amp circuit that will take a voltage as an input and will amplify it with a gain of C. The magnitude of the current that flows through the feedback resistor must be between 0.1 mA and mA when the output from the amplifier is the maximum voltage possible (for your power supply voltages). The input voltage source must be named V3. The named net for the input voltage should be Vin and named net for the output voltage must be Vout. The feedback resistor must be named Rf. [20 marks] 4. Design a circuit that takes 3 voltages as inputs (a, b, and c) which has an output that is equal to D(Ea - Fb) + Gc. The three voltages sources used for the input voltages should be named VA, VB and VC and they should be connected to your circuit via named nets, named Va, Vb and Vc. [20 marks] 5. Create a voltage source labelled V3 and connect the positive terminal to a named net called Vin. Set a source resistance for the voltage source by right clicking on it and entering a value into the Series Resistance box. Voltage Source - V3 DC value [V]: Series Resistance [22]: 2000 OK Cancel Advanced X Figure 1: Setting the Series Resistance of V3 (for example to 2000 ohms). The value you use should be between 1000 and 10000 ohms. This setting will give the voltage source an output resistance. Looking from the point of view of an amplifer with an input of Vin, this is the also the source resistance. Design a circuit that will amplify the signal Vin with a gain of H dB. The gain of the circuit must not depend upon the value of Series Resistance chosen above. That is, if the Series Resistance is changed, the value of the output voltage should remain the same or almost identical. The named net for the input voltage should be Vin and named net for the output voltage must be Vout. Only use integer (whole number) values of Ohms for your resistances (round the value you require to 0 decimal places). [20 marks] 6. Design a circuit where the output voltage will be the difference between two input voltages, connected by named nets Va and Vb (the sources to be named VA and VB respectively), multiplied by J. The output, Vout, should be J (Vb - Va). The output should also be independent of the source resistances of the inputs (see Figure 1 for setting source resistances). It is also a requirement that the gain of the circuit be adjustable using only one resistor, which must be labelled Rg. The named net for the output voltage must be Vout. The common mode rejection ratio (CMRR) must be infinite. [20 marks]See Answer
Q18:Question 2 (40 marks) With reference to Fig. 2, (a) write a formula (symbols only) for the Thévenin equivalent voltage and resistance of the subcircuit to the left of nodes 2 and 0 (i.e. Vs, R3 and R4), wwwww (b) calculate the numerical value of the voltage e3 at node 3 at time 1 ms and (c) calculate the numerical value of the voltage e3 at time 1 s, when R1 = R3 = (1000 + y) 22, R2 = R4 = (2000+5) 2, C1 = (1000 + E) nF, and C1 is initially discharged (i.e. the voltage e2 at node 2 is zero at t = 0). Vs is a piecewise-linear voltage source in which Vs = 0 for t < 100 us, and Vs = 1 V for tz 100 μs. www Vs Vth www. Rth www. e3(1ms) e3(1s) R3 R4 R1 Figure 2 0 R2 OPAMP C1 3 30% 40% 20% [+]See Answer
Q19:Question 2 (40 marks) With reference to Fig. 2, (a) write a formula (symbols only) for the Thévenin equivalent voltage and resistance of the subcircuit to the left of nodes 2 and 0 (i.e. Vs, R3 and R4), wwwww (b) calculate the numerical value of the voltage e3 at node 3 at time 1 ms and (c) calculate the numerical value of the voltage e3 at time 1 s, when R1 = R3 = (1000 + y) 22, R2 = R4 = (2000+5) 2, C1 = (1000 + E) nF, and C1 is initially discharged (i.e. the voltage e2 at node 2 is zero at t = 0). Vs is a piecewise-linear voltage source in which Vs = 0 for t < 100 us, and Vs = 1 V for tz 100 μs. www Vs Vth www. Rth www. e3(1ms) e3(1s) R3 R4 R1 Figure 2 0 R2 OPAMP C1 3 30% 40% 20% [+]See Answer
Q20:A 1k 12V 1k 3.3K RL www Vo m 1:47K 2.2K 5V B Prelab la: Determine Voc (Open Circuit Voltage) In the space provided below, find Vth (Voc) as seen by the load resistor R. You will need to remove R and use mesh or nodal analysis to determine the theoretical open circuit voltage between nodes A and B./nTheoretical VOC = V Prelab Ib: Determine Isc (Short Circuit Current) Remember that Isc is the short circuit current which is present when a wire is connected from where the load resistor was removed. In the space provided below, determine the theoretical Isc./nTheoretical Isc = Prelab Ic: Determine RTH (Thevenin Equivalent Resistance) Use the values of Voc and Isc found in Prelabs 1A and 1B to determine the value of R.TH. R TH=VOC/ISC Theoretical RTH = Ω A/nR (Load Resistor Value) 220 Ω 330 Ω 2.2k Ω 3.3kΩ 4.7k Ω 47k Ω 100k Ω Theoretical Vo (Output Voltage) Theoretical Io (Output Current)See Answer

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