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Q1: EEEE1004: INFORMATION AND SYSTEMS 2023/24 Topic 3 - Semiconductor Devices University of Nottingham UK CHINA MALAYSIA Coursework 3: Simulation & Design of Diode Circuits using LTspice Within this coursework, you will again use LTspice, however this time the focus will be on 'Semiconductor Devices', more specifically, the simulation and design of diode circuits. There are four questions in total to complete, with the marks for each part shown. Ensure that you carefully follow what you are asked to do and what to include in your document. Your final mark for this assignment will contribute 15% to your final grade for the 'Information and Systems' module. The coursework assesses elements from the 'Semiconductor Devices Lectures 1-2' and 'Seminars 1-2' with some additional context provided in 'Lecture 3'. In addition to this, for the last part of Question 4, a new diode application is introduced which is only needed for this coursework. Instructions You should prepare a single word-processed document with the solutions containing your designed circuit schematics, relevant outputs i.e. graphs or simulation text, and your interpretation of these results when requested. The requested circuit diagrams and graphs must come from your LTspice simulations which you will also be required to submit alongside your document. For any given question, the maximum mark that can be achieved will be 50% if the corresponding LTspice file is not provided. For submission, your document must be converted to a single PDF file. Name this file 'EEEE1004-CW3-########.pdf, where '########'’ is your student ID. Within your document, number all pages and give your solutions to each question sequentially, making sure it is clear which question and part you are answering. As this is the second coursework involving LTspice, less direction is provided, so you may wish to refer back to the LTspice seminar or feedback from Coursework 2 to ensure that you follow good practice when completing circuit layouts and labelling components. Ensure that you show all of your working out for any calculations, think about the accuracy to which you are quoting values and remember to give appropriate units where needed. Throughout the coursework document, you will be instructed to create six schematics, which should be appropriately named as directed. During each question, you will modify and add to your circuits, but you are only required to submit the final version of each schematic i.e. up to the point before you create the next schematic file. Your submission is due before the published deadline: Tuesday 5th March 2024, 15:00 (UK time). Submission is via Moodle only – you can find the place to do this on the EEEE1004 Moodle page. Your submission must consist of a total of 7 files: 1 x PDF file and 6 x ASC files from LTspice. The submission box on Moodle will only accept a maximum of seven files and the only permissible types are PDF and ASC – do not try to make and submit a ZIP of your work. Ensure that you click the submit button so that your work is submitted — drafts will not be marked and clicking submit after the deadline will result in a late penalty. - This coursework is an individual piece of work. Please remember your Academic Misconduct training. If you are unsure about what constitutes Academic Misconduct, please ask! If they are needed, you should use the following values for physical constants in your calculations: Electronic charge (magnitude): q=1.60 × 10-¹⁹ C Boltzmann constant: k = 1.38 × 10-23 JK-1 1 EEEE1004: INFORMATION AND SYSTEMS 2023/24 Topic 3 - Semiconductor Devices i Question 1 [30 marks] In this question, you will investigate the I-V characteristics of a 1N914 diode. The easiest way to get this component is as follows: University of Nottingham UK CHINA MALAYSIA Use the diode component from the toolbar and place it on your schematic. Right click on the diode you have placed and use the 'Pick New Diode' option. Choose the correct diode from the list. a) Create a new schematic called 'EEEE1004-CW3-########-Q1.asc' and draw a series circuit consisting of a 5V DC voltage source, followed by a 1000 resistor and then a 1N914 diode. Use the 'Label Net' feature to label the voltage across the diode as VĎ. Remember that in order for LTspice to work, you must always include a ground. Include an image of your circuit schematic in your document. [3 marks] b) Perform a DC operating point (DC op pnt) simulation and include the copied text from simulation output in your document. From this output, identify the two values that represent the operating point (Vo, la) of the diode, i.e. the voltage across the diode and the current through the diode. Write this operating point in your document, and then use it to calculate: i. ii. iii. The reverse saturation current, lo, of this diode. Assume n = 1 and T = 293 K. The static resistance of this diode at its operating point. The dynamic resistance of this diode at its operating point. Remember: 25// [mA]. Show all of your working and answers in your document. [8 marks] c) Now adjust the DC voltage source so that it performs a sweep of the input voltage from OV to +10V. Choose an appropriate increment for the sweep voltage. Plot the forward biased diode characteristic and include this plot in your document. [3 marks] Hint: You are asked to plot the diode characteristic from the circuit that you have simulated. The diode characteristic is just one line on your graph, and this should be of the diode current, lò, against the diode voltage, VĎ - not the supply voltage to your circuit. When you first see the plot window after running your simulation, unfortunately the x-axis shows the supply voltage which you have just swept from OV to 10V. LTspice assumes that this is what you want, but, of course, this is not the case - you want to have the diode voltage on the x-axis. You can change the x-axis to be the diode voltage as follows: Right click on the x-axis label. A window for specifying the horizontal axis parameters will appear. The 'quantity plotted' box will say V1 (or whatever name you have given the voltage source which is the supply voltage to your circuit). 2 Change the 'quantity plotted' to 'V(vd)' where 'vd' is the net name you gave to the diode voltage. This tells LTspice that you want to plot a voltage 'V' which is referenced as 'vd'. ● You can then add the single trace you need to the plot, i.e. the diode current. EEEE1004: INFORMATION AND SYSTEMS 2023/24 Topic 3 - Semiconductor Devices ii. d) Now you will investigate how the diode operating point changes as we move small amounts 'away' from the operating point which you have found. Use a cursor on your forward bias characteristic to find values for the diode current, at the following values of diode voltage, where Vo is the diode voltage at your original operating point - as found in b) above: i. VQ - 10mV VQ + 10mV iii. VQ-50mV iv. VQ + 50mV Tabulate the above values of diode voltage (in mV) and their corresponding currents (in mA) in your document. [6 marks] University of Nottingham UK CHINA MALAYSIA e) Using the values in your table, calculate the change in current and hence, the dynamic resistance about the original diode operating point for the following diode voltage swings: i. ± 10mV ii. + 50mV Show all of your working and answers in your document. Compare the two new values of the dynamic resistance, from e) i) and e) ii) above, to each other and then compare them to the value found in b) iii). Comment on any differences. [6 marks] f) Now adjust the DC voltage source so that it performs a sweep of the input voltage from -10V to OV. Choose an appropriate increment for the sweep voltage. Plot the reverse biased diode characteristic and include this plot in your document. From the plot, determine the diode reverse saturation current, lº. Compare this to the value found in b) i) and comment on the potential origins of any differences. [4 marks] Question 2 [30 marks] In this question, you will investigate a full-wave, or bridge, rectifier, based on 1N914 diodes. a) Create a new schematic called 'EEEE1004-CW3-########-Q2.asc' and construct a full-wave rectifier. Use four identical 1N914 diodes and a 1k0 load resistor. Include a voltage source in your circuit, instead of the transformer shown in the lecture, and label this voltage 'Vin'. The input voltage should be a 30V sinusoidal signal with a frequency of 1Hz and a DC offset of OV. Label the voltages at either end of the load resistor as 'Va' and 'V'. Include an image of your circuit schematic in your document. [5 marks] b) Run a transient simulation for 5s. Create a plot with two independent panes that show: i. the input voltage, Vin. the voltage output across the load resistor, i.e. the difference between 'V₂' and 'V', remembering that this output should be positive. ii. Include this plot in your document. Explain why the peak voltage of the output is less than peak positive voltage of the input. [6 marks] 3 EEEE1004: INFORMATION AND SYSTEMS 2023/24 Topic 3 - Semiconductor Devices ● Hint: You are asked to plot the difference between two voltages; which should be called 'Va' and 'V' and placed at either end of the load resistor. You generate such a plot as follows – note that the below instructions assume you want to plot V₁-V, but you may need to invert this depending on which end of the resistor you have labelled with which label: T University of Nottingham UK CHINA MALAYSIA Run your simulation. Right click on the plot window and choose 'Add Traces'. Note the box at the bottom of this window that says 'Expression(s) to add'. Click on 'V(va)' in the list and it should appear in the 'Expression(s) to add' box. Type a minus sign in the 'Expression(s) to add' box. Click on 'V(vb)' in the list and it should appear in the 'Expression(s) to add' box after the minus sign which you have just typed. Click 'OK' and you should see your plot with the label 'V(va)-V(vb)' at the top. i. c) Modify the input voltage so that the amplitude is 3V. Perform another transient simulation that runs for 5s. Create a plot with two independent panes that show the input voltage and the output voltage across the load resistor. Include this plot in your document and then answer the following questions. [8 marks] ii. Estimate the turn on voltage of the 1N914 diode. Clearly explain how you determined your value. Explain why, in this second simulation, there are significant periods where the voltage across the resistor is zero. Explain why these periods of zero output voltage are much shorter, almost zero, in your first simulation. d) You will now investigate the addition of a smoothing capacitor in parallel with the load resistor. Experiment with capacitor values of 100µF, 470µF and 2200µF. Include plots of the output voltage (the voltage across the load resistor) for each capacitor value in your document. For each of the investigated capacitors, use the cursor to determine the ripple of the output voltage. The ripple is defined as the difference between the maximum of the output voltage and the minimum of the output voltage, once it is a periodic signal i.e. ignore the initial charging period of the capacitor. Include a table, in your document, that summarises your values for the voltage ripple, to the nearest millivolt, for each capacitor value. [7 marks] e) To further reduce the ripple, several capacitors can be used. For a given DC power supply application in this question, the maximum allowable ripple is 70mV. Determine how many 2200μF capacitors need to be implemented in the circuit in order to achieve this. Include an image of your circuit schematic in your document. Also include a plot of the output voltage, making sure that it clear to see that the output voltage ripple indeed meets the specification i.e. think about an appropriate scale for displaying the data. [4 marks] EEEE1004: INFORMATION AND SYSTEMS 2023/24 Topic 3 - Semiconductor Devices Input Question 3 [30 marks] In this question, you will design several stages to manipulate a 1V sinusoidal input into an output which resembles a 3.3V square wave. The output is then used to drive two light emitting diodes (LEDs) so that both 'blink' periodically. Figure 1 shows each stage as well as the approximate 'ideal' signal which would be observed at each stage. For this question, you will design each stage in isolation, you do not need to combine the circuits designed in the three parts below. m Amplification 11 -11 Clipping 3.3 i 0 University of Nottingham UK CHINA MALAYSIA LO Figure 1: Illustrative Example of Each Stage & the Approximate Waveform Outputted from One Stage & Inputted into the Next A multi-stage design, such as the one illustrated above, could be used in place of a comparator circuit. The amplification stage must have a significant gain so that once the signal is ‘truncated' to resemble a square wave, the transition time between the 'high' and 'low' voltages is minimised i.e. each pulse resembles a square rather than a trapezoidal shape. 5 Output Part 1: Light Emitting Diode Circuit [10 marks] The LED component which you will use for this stage is the ‘QTLP690C' diode. This can be found using the same method detailed in Question 1. a) Create a new schematic called 'EEEE1004-CW3-########-Q3_Part_1.asc' and draw a series circuit; consisting of a 3.3V DC voltage source, followed by a 70º current limiting resistor and then an LED. Use the 'Label Net' feature to label the voltage across the diode as V₁ and the supply voltage as Vs, then run a DC operating point simulation. Include both an image of your schematic and the copied text from the simulation output in your document. [3 marks] b) Add a second identical branch to your circuit i.e. a second current limiting resistor and LED in parallel with the first branch. Adjust the voltage source so that it outputs a square wave. To do this, right-click on the voltage source → 'Advanced' and select 'PULSE'. Enter the appropriate parameters so that the signal has a minimum voltage of OV, maximum voltage of 3.3V, no delay time, 0.01ms of rise and fall time, a period of 2ms and is on for 1ms. Run a transient simulation for 10ms and include a single plot of the voltage across the LED and the supply voltage in your document. Use the cursors to verify that this matches your output in a). [2 marks] c) Calculate the voltage across the LED, VD, and the voltage across the current limiting resistor, VR - you must not perform a direct measurement to obtain these values. Verify that these values match the simulation by plotting VS, VR and V₁ on a single plot and include this in your document - ensure that the traces are named appropriately. You may reorder the schematic if you require, however you must not add or remove components. [5 marks]See Answer
Q2: Prelab Part 1 Please follow all rules, procedures and report requirements as described at the beginning of the document entitled ECE 220 Laboratory 1. Always wear your safety glasses when performing your lab experiments. This part and the next part reinforce the circuit analysis techniques that we have learned in class. V1 Use mesh analysis to solve the circuit shown below in Figure 1. For the purpose of your analysis, assume that the LED is forward biased (turned on). As before, we will approximate its behavior by a constant voltage drop of 2.1 V. Hint: only two equations and two unknowns are required. a) Calculate i₁, I2, I3, V₁, V2, and 13. 12.5 mA( LED ECE 220 Laboratory 2 Mesh and Node Analysis, AC Sources, and d'Arsonval Meters KH T 470 Ω V2 47 Ω Michael W. Marcellin 100 Ω V3 i[1002 [>100 2 Figure 1. Solve using mesh analysis. We will now verify your calculations using PSpice. Start PSpice and create a new project as you did for the PSpice homework and Lab 1. Draw the circuit from Figure 1, as shown below in Figure 2. Again, we use three D1N4002 diodes in place of the LED. Note that the bottom node in Figure 1 has been labeled as the reference node (0 V). As discussed in the PSpice homework and in class, any essential node can be chosen as the reference node. The PSpice ground should be thought of as the reference node. This can be seen via a comparison of Figures 1 and 2. D1 D2 D3 11 D1N4002 D1N4002 D1N4002 + 12.5mAdc R1 ww 470 www R3 100 R5 ww 47 R2 ww 100 Figure 2. PSpice schematic. www Click PSpice -> New Simulation Profile Enter a name for this profile Click Create R4 We will use PSpice to find the DC voltages and currents in the circuit, as we did in the PSpice homework. Prelab Part 2 100 A new window will open. You might have to look at the icons at the bottom of the screen to find it. In the drop down menu entitled Analysis type:, choose Bias Point This tells PSpice that we are going to compute the static DC values of voltages and currents in the circuit. Check the box below the drop down menu that says "Save Bias Point." Click "OK" Click PSpice -> Run A new window will open. You may need to look at the icons on the bottom of the screen to find it. If there are no errors, you may close this window and return to your schematic. Near the top of the screen there are 2 green buttons, labeled V and I, respectively. Use these buttons to view the currents and voltages in your circuits. The values should be slightly different than your calculated values. b) Print a copy of your schematic with the voltage labels turned on (File -> Print). c) Print a copy of your schematic with the current labels turned on (File -> Print). d) Why do the PSpice values differ (slightly) from your calculations? Use node analysis to solve the circuit shown below in Figure 3. Hints: 1) Again, only two equations and two unknowns are required. 2) Recognize that 2sin(200ât) = 2cos(200ât — ñ/2) and use complex phasor analysis. a) Calculate i₁(t), i₂(t), i3(t), v₁ (t), v₂(t), and v3(t). v=2sin (200πt) V VOFF = 0 VAMPL = 2 FREQ=100 AC = V1 V1 द् 1.5 ΚΩ V2 R1 ww 1.5k 470 Ω 1 ΚΩ ia|é1.5 ka Figure 3. Solve using node analysis. Again, we will verify your calculations using PSpice. Start a new PSpice project as you have done before, and draw the circuit of Figure 3. The PSpice part name for the sinusoidal voltage source is VSIN. Set VAMPL=2, and FREQ=100, which is consistent with the sin in Figure 3. In that figure the angular frequency w = 200π radians/second. You must input the frequency to PSpice in Hz. Since w= 2πf, we have f = 100 Hz. VOFF is an optional DC offset. Set this to 0. Add voltage markers (PSpice -> Markers -> Voltage Level) at each of the three nodes of interest, as shown in Figure 4 below. PSpice -> New Simulation Profile Enter a name for this profile Click Create R3 ww 470 V3 ia|ફૅ2.2 ka R4 1.5k R2 1k ww R5 2.2k Figure 4. PSpice schematic. We will use PSpice to plot v₁ (t), v₂(t), and v3(t). We have not done this type of analysis in PSpice before. Click A new window will open. You might have to look at the icons at the bottom of the screen to find it. In the drop down menu entitled Analysis type:, choose Time Domain (Transient) This tells PSpice that we are going to create a time domain plot of the values associated with the markers in the circuit. Enter the following parameters: Run to time: 25m Maximum step size: 0.1m Click "OK" This tells PSpice we want to create 25 miliseconds worth of data for our graph, with data points no more than 0.1 miliseconds apart. Click PSpice -> Run A new window will open. You may need to look at the icons on the bottom of the screen to find it. This window should contain a time plot (of duration 25 ms) showing the three voltages associated with the markers. These plots should agree with your calculations in a) above. b) Print the plot. Prelab Part 3 In class, we learned how to make a simple (but not very good) voltage meter using a d'Arsonval meter movement. The circuit diagram for such a meter is shown below in Figure 5. This meter includes (of course) a d'Arsonval meter movement and a resistor. The purpose of the resistor is to limit the current through the meter movement. The meter movements that we have in the lab have a maximum current of imax = 1 mA. The internal resistance of the meter movements is Ra 155 . You are to design a volt meter that gives full scale reading (100% deflection of the meter needle) at 5 V. a) Calculate the required value for RA. = RA Figure 5. Voltage meter. The amount of deflection of the meter needle will now indicate the voltage being measured. Since we have designed for full (100%) deflection at 5 V, 25% deflection indicates 1.25 V, 50% deflection indicates 2.5 V, etc. It is worth noting that the current flow is actually what causes the needle deflection. Since imax 1 mA, 0.25 mA will cause 25% deflection, 0.50 mA will cause 50% deflection, etc. = We will now verify the operation of your meter design using PSpice. We will "connect" your meter to a voltage source. We will then sweep the value of the voltage source from 0 to 5 V and see that the current through the meter movement varies linearly from 0 to 1 mA. Create a new project in PSpice and draw the circuit shown in Figure 6 below. We model the meter movement as a resistor with value Rd. 3 {M} V1 Put the value you RA calculated for R here. Figure 6. Meter simulation. Rd www PARAMETERS: V = 5.0 155 We will now sweep the voltage source using a variable V. This is very similar to when we did a sweep of the pot value in Lab 1. If you have not already done so, place the "Part" PARAM, which appears as PARAMETERS in Figure 6. Double click on PARAMETERS to open the Property Editor Spreadsheet. Click the "New Property" button in the upper left portion of the screen. A new screen will open. Enter V in the field labeled Name:. Below that enter 5.0 for Value:. Click "OK" Click on the V Heading (that we just created) in the Property Editor Spreadsheet. You may need to scroll to the right or left to find this heading. Now click the button above labeled "Display..." A new window will open. Click the button for Name and Value and click "OK" Return to the schematic by clicking the tab marked "PAGE1" Below the PARAMETERS part, you should now see V=5.0 as in Figure 6. We now need to associate our parameter V with the voltage source. Double click carefully on the value of the voltage source (probably OVdc). A window will open. Replace the value OVdc with {V} Don't forget the {} braces. Click OK. On the circuit symbol for the voltage source, you should now see {V} as in Figure 6. Here we will specify the parameters to "sweep" the value of V from 0 to 5 in steps of 0.1. Click PSpice -> New Simulation Profile Enter a name for this profile Click Create A new window will open. You might have to look at the icons at the bottom of the screen to find it. In the drop down menu entitled Analysis type:, choose DC Sweep. Enter the following parameters: Sweep Variable: Global parameterSee Answer
Q3: 6.1. Simulating the IF filter in LTSpice In this part of the homework, you will simulate the IF filter of the NorCal40A radio using LTSpice. The filter architecture is given below. 750.1 pF HOHOH 750.1 pF 790 pF HOHT 丰 Q1. Draw the equivalent circuit diagram, as simplified as possible, and explain how this works as a band-pass filter. Q2. Simulate the filter from 4-6 MHz using a 50 2 impedance at the output (scope) and a 50 2 generator at the input. Note that the crystals are modeled by a series RLC circuit in parallel with a capacitor Cp (Fig. 5.13 in your textbook) with the following parameters: L-20 mH, C-52.5 fF, R=5 2 and Cp 100 pF. (Do not simulate the simplified ladder circuit from the previous question.) Attach a plot of the output across the frequency range 4-6 MHz. Q3. What is the simulated pass-band bandwidth and the frequency at which the filter has minimal loss? Pass-band bandwidth: Frequency of minimum loss: Q4. How does the filter response change if the capacitors that are connected to the generator and scope change from 750.1 pF to 400 pF and the capacitors to ground change from 790 pF to 460 pF? Attach a plot if helpful. Q5. Change the capacitors back to their original values. How does the filter response change if the frequency of the edge crystals increases by 5% and the frequency of the middle crystals decreases by 5%? Attach a plot if helpful.See Answer
Q4:A 1k 12V 1k 3.3K RL www Vo m 1:47K 2.2K 5V B Prelab la: Determine Voc (Open Circuit Voltage) In the space provided below, find Vth (Voc) as seen by the load resistor R. You will need to remove R and use mesh or nodal analysis to determine the theoretical open circuit voltage between nodes A and B./nTheoretical VOC = V Prelab Ib: Determine Isc (Short Circuit Current) Remember that Isc is the short circuit current which is present when a wire is connected from where the load resistor was removed. In the space provided below, determine the theoretical Isc./nTheoretical Isc = Prelab Ic: Determine RTH (Thevenin Equivalent Resistance) Use the values of Voc and Isc found in Prelabs 1A and 1B to determine the value of R.TH. R TH=VOC/ISC Theoretical RTH = Ω A/nR (Load Resistor Value) 220 Ω 330 Ω 2.2k Ω 3.3kΩ 4.7k Ω 47k Ω 100k Ω Theoretical Vo (Output Voltage) Theoretical Io (Output Current)See Answer
Q5: In this tutorial assignment, you will learn to perform a simple circuit simulation in PSpice. You will learn more advanced techniques in your laboratory assignments. PSpice is a circuit simulator. In the old days, you had to enter your circuit diagram information by hand as a netlist. Nowadays, we have a graphical interface to simplify the entering of a circuit diagram. This graphical interface is called Capture. We really interact mostly with Capture, but the whole package is often still called PSpice for historical reasons. ECE 220 PSpice Homework Voltage Divider and Current Divider Michael W. Marcellin You can use the computers in room ECE 232 to do all of your PSpice work. These computers are supported by the IT staff. They ensure that all software works properly. If you so choose, you may download PSpice and install it on your own computer. You can get instructions to install PSpice on your computer from the ECE 220 website by following the link for Lab Resources. Voltage Divider The first circuit we will simulate using PSpice is a simple voltage divider. This circuit is shown below in Figure 1. 12 V 3 ΚΩ m Figure 1. Voltage divider. 1kΩΣ01 +51 1k 1k+3k From class, we know (or will learn) that v₁ = - 12 = 3 V. There is really no reason to simulate this simple circuit other than to practice PSpice where we already know the answer, and can easily check our work. To begin, click Start -> Cadence Release 17.2-2016 -> Capture CIS (Lite) In some versions of PSpice, a window may open with two choices. If this happens, choose Allegro PCB Design CIS L Note: You may see a different version number than "17.2." To open a new project, click File -> New -> Project... A new window will open. Type a name for your project. Click the button for "Analog or Mixed A/D" Choose a location to save your work and click "OK" Another new window will open, click the button for "Create a blank project" click "OK" A white screen with a grid of black dots will appear. You draw your circuit on this screen. To place components on the screen, click Place -> Part... A new panel will open on the right portion of the screen. **** Begin to type a part name (see useful part names below). The list of parts will automatically scroll. When you see the name of the part you want, double click it. Your mouse curser will change to reflect the circuit symbol you have chosen. You can rotate the symbol by pressing the 'r' key on the keyboard. After you get the desired rotation, you place the rotated part on the screen by clicking at your chosen location. When you are finished, press 'esc' on the keyboard. You may then select a different part to place. Useful parts for this exercise include: VDC (voltage source) - ignore/Design Cache, /ANALOG, /BREAKOUT, etc. These are library names. R (resistor) Let's begin by placing a voltage source on your schematic. The circuit symbol that PSpice uses for a voltage source is shown below in Figure 2. Note that this circuit symbol is different than the one we use in class, but is commonly used in other textbooks. positive pin value **** OV dc- V₁ name negative pin Figure 2. PSpice circuit symbol for voltage source. Once you place a voltage source on your schematic, be sure to press esc on your keyboard. You can then adjust the parameters of the voltage source. There are 5 attributes that you can select on the voltage source: the name, the voltage value, the positive voltage pin, the negative voltage pin, and the voltage source symbol itself. For this circuit element, you will usually only change the voltage value (required), and the name (optional). Double click carefully on the voltage value. A new window will open where you can change the voltage value from 0Vdc to 12Vdc as needed for the circuit of Figure 1. If there are no parts, go to the Lab Resources page of the class website and click the link "What to do if there are no parts in PSpice." Follow the instructions you find there. A word about units. Pay close attention to this. There are a couple of opportunities to make mistakes. PSpice uses the following abbreviations for unit prefixes: Prefix femto pico nano micro milli kilo mega giga tera Abbreviation f р n u m k meg g t The ones that will give you trouble are micro, milli, and mega. PSpice is not case sensitive. So, "m" is not micro - it is milli "M" is not mega - it is milli PSpice ignores the units themselves (or anything else that may come after the prefix). For example, for a current source, 12mA dc is the same as 12m. One case where this can get you into trouble is with a capacitor. Think about 1F... How will PSpice interpret this? Is it 1 Farad? Nope... it is the same as 1fF which is 1 femto-Farad. Now place the resistors on your schematic and change their values to those shown in Figure 1. Note: You can place both resistors without pressing esc in between. To wire your parts together, click Place -> Wire Click on a device pin to begin wiring. Move the mouse to an intermediate location and click to put a bend or a corner in a wire. Click on another device pin or wire to complete the connection. Be very careful that your wires actually make a connection. Hint: watch for a red dot. Important Note: In PSpice, every circuit must have a ground. The simulation will not function without a ground. To include a ground, click Place -> Ground A new window will open. Choose one of the grounds named 0 (e.g., 0/SOURCE, 0/CAPSYM, 0/Design Cache) and click "OK" None of the other choices for ground will work. If this ground is missing, see the instructions for installation of PSpice libraries mentioned earlier in this document. Place a ground on your schematic and connect it as shown below in Figure 3. This “ground" should be thought of as a point in the circuit that we are defining to be 0 V. We can put this point anywhere in the circuit that we choose. For now, place it as shown in the figure. A good analogy for the PSpice 0 V ground can be explained in terms of the (arbitrary) reference point used to define altitudes. Altitudes do not make sense without a reference. For example, if I want to talk about the altitude of the ceiling in my room, I could say that the ceiling is 10 feet above the floor. I could also say that it is 2,410 feet above sea level. In the first case, the reference (0 feet) is the floor. In the second case, the reference (0 feet) is sea level. Voltages in PSpice are much the same. They are specified with respect to the reference (0 V) defined by the ground. 12Vdc V1 R1 ww 3k R2 1k Figure 3. PSpice schematic for the voltage divider of Figure 1. More notes: There are many other ways to accomplish the tasks described above. For example, see the icons on the right portion of the screen. There are also many hot-keys. We mentioned ‘r’ above which rotates parts. Additionally, ‘v’ will flip a part vertically, while ‘h’ will flip a part horizont12ally. Pressing 'g' will open the window for placing grounds. To zoom in, press 'i'. To zoom out, press ‘o'. You can drag parts on the schematic to relocate them. You can also drag labels, values, etc. Any item can be removed from the drawing by clicking it and pressing delete on the keyboard. You can redraw the screen to clean up any extraneous marks by pressing 'F5'. Let's now use PSpice to find the voltages and currents in our circuit. Click PSpice -> New Simulation Profile Enter a name for this profile (e.g., VDiv) Click Create A new window will open. You might have to look at the icons at the bottom of the screen to find it. Here we go. Click In the drop down menu entitled Analysis Type:, choose Bias Point This tells PSpice that we are going to compute the static DC values of voltages and currents in the circuit. Check the box below the drop down menu that says "Save Bias Point." Click "OK" PSpice -> Run A new window will open. You may need to look at the icons on the bottom of the screen to find it. For this simple simulation, the only thing of interest is the text in the bottom center which may give you some hints if you have errors in your circuit drawing. If the simulation fails to run, check your work. Common errors include: no ground, wrong ground (see discussion on grounds above), wires/pins not connected properly (upon failure, PSpice usually will draw some circles on your schematic to highlight this latter problem). You may close this window and return to your schematic. Near the top of the screen there are 2 green buttons, labeled V and I, respectively. Click the button labeled I a few times. It turns on and off labels near one pin of each circuit element. This label tells you the current flowing into that pin of the device. Note carefully the position of these labels and make sure you understand the sign convention. When you are finished, leave the labels turned off. Repeat with the button labeled V. This turns on and off labels that tell you the voltage value at each node in the circuit. These voltages are given with respect to ground, which is defined to be 0 V. If you want to know the voltage across a circuit element, you can take the difference between 2 node voltages. For example, the voltage the across the 1 k resistor is 3 - 0 = 3 V, with positive polarity on the top, as expected. Similarly, the voltage across the 3 kn resistor is 12 - 3 = 9 V, with positive polarity on the left. Make sure you understand this. Think about KVL. a) Print a copy of your schematic with the voltage labels turned on (File -> Print). Experiment with moving the ground to a different node. Recall from the discussion above that this defines a new reference for O V. Run the simulation again (PSpice -> Run). Make sure you understand how the voltage labels change. Note that the voltages across the individual circuit elements do NOT change. Current Divider Repeat the steps above for the current divider circuit shown below in Figure 4. The part name for the current source is IDC. 11 12m Adc ww R1 3k www R2 1k Figure 4. Current divider circuit. b) Print a copy of your schematic with the current labels turned on. Turn in the printouts from a) and b) above in class. One last note: You can easily copy/paste drawings from PSpice into MS Word or Powerpoint. To copy a drawing of interest, stretch a rectangle around it and then press ctrl-c.See Answer
Q6:Question 2 (40 marks) With reference to Fig. 2, (a) write a formula (symbols only) for the Thévenin equivalent voltage and resistance of the subcircuit to the left of nodes 2 and 0 (i.e. Vs, R3 and R4), wwwww (b) calculate the numerical value of the voltage e3 at node 3 at time 1 ms and (c) calculate the numerical value of the voltage e3 at time 1 s, when R1 = R3 = (1000 + y) 22, R2 = R4 = (2000+5) 2, C1 = (1000 + E) nF, and C1 is initially discharged (i.e. the voltage e2 at node 2 is zero at t = 0). Vs is a piecewise-linear voltage source in which Vs = 0 for t < 100 us, and Vs = 1 V for tz 100 μs. www Vs Vth www. Rth www. e3(1ms) e3(1s) R3 R4 R1 Figure 2 0 R2 OPAMP C1 3 30% 40% 20% [+]See Answer
Q7:Question 2 (40 marks) With reference to Fig. 2, (a) write a formula (symbols only) for the Thévenin equivalent voltage and resistance of the subcircuit to the left of nodes 2 and 0 (i.e. Vs, R3 and R4), wwwww (b) calculate the numerical value of the voltage e3 at node 3 at time 1 ms and (c) calculate the numerical value of the voltage e3 at time 1 s, when R1 = R3 = (1000 + y) 22, R2 = R4 = (2000+5) 2, C1 = (1000 + E) nF, and C1 is initially discharged (i.e. the voltage e2 at node 2 is zero at t = 0). Vs is a piecewise-linear voltage source in which Vs = 0 for t < 100 us, and Vs = 1 V for tz 100 μs. www Vs Vth www. Rth www. e3(1ms) e3(1s) R3 R4 R1 Figure 2 0 R2 OPAMP C1 3 30% 40% 20% [+]See Answer
Q8: EEEE1004- Coursework #2 Simulation and design of Op-Amp circuits using LTspice In this coursework you will design and simulate some of the op-amp circuits that have been covered in the module (EEEE1004). The set of designs each student will make will be different as all students will receive different design parameters. The design parameters are referred to in this document as letters of the alphabet, and are highlighted, for example A. The value of A can be found from the spreadsheet provided on Moodle, which has a set of values for each student ID. This coursework forms 15% of the mark for the EEEE1004 module. Submission Your coursework submission will consist of a single PDF file (it suggested that this is created using Microsoft Word), containing your working for each of the questions. The individual .asc files (which contain your circuits) that you have created while doing your coursework must also be submitted. These files will be marked by automation of the simulation process and must be named in the following format, with the question number that it relates to, for example, 'Question 1.asc'. Ensure that you label the nets as described in the question. Failure to do so will limit how many marks you will receive. How will this work be marked As part of the automation of the simulation used for marking, different input voltages and currents will be set and voltages and currents around the circuit will be checked to ensure they match those expected from the input parameters given in the task. Full marks will be given to for a task if the simulation meets the requirements given in the question, this includes using the labels and device names described in the text. If the simulation does not meet the requirements, then partial marks are available. The working presented in your report is worth 50% of the marks, with the simulation aspect being worth the other 50%. As mentioned above, the simulation files will be marked by automating the simulation process. Any deviation from using the labels and device numbering required will require manual intervention and the loss of one mark per intervention required (down to 50% of the question mark - ie down to 0% for the simulation aspect of the question). If you show clear and correct working as part of your submission, but fail to submit a working simulation file, the marks will be limited to 50% of the marks available for that question. Partial marks will also be given for your working up to 50% of the marks available for that question. If the simulation presented matches your working, but your working is incorrect, the maximum mark available for the simulation part of the question will not be greater than the marks obtained from the working. If an incorrect amplifier type is demonstrated a mark of zero will be awarded for that question. You should assume that any value of resistance is available and must not limit yourself to using Standard Resistor Values. It is anticipated that you will check that the simulated circuit you have produced meets the design requirements given in the question, that is you can check your own work meets the design requirements before submission through simulation. Note: You are simulating a real op-amp (rather than an ideal one) and therefore the output values will not be exactly what you expect but will very close to the expected output - within 0.02%. Do not try to adjust your resistor values away from the theoretically correct values to get a perfect result. Hints Sometimes hints/reminders are given on how to achieve a task using LTspice, for example labelling a net. The keyboard shortcut will be shown like so, F4, meaning the F4 key on the keyboard should be pressed. How to achieve the same task using the menu bar may also be given, for example "Edit→Label Net", means click on 'Edit' on the menu bar followed by 'Label Net'. Tasks For each task, show your working in your document. You do not need to use an equation editor or similar, so long as the mathematics presented is clear and easy to follow. Suitably cropped photos/scans of handwritten equations inserted into the document are acceptable. When an op-amp is required, only use the LT1097 Op-Amp (this can be found as a component in the 'Opamps' folder in the 'Select Component Symbol' window, found using F2 or “Edit⇒Component”) for this coursework. Unless specified, for each task, the circuit needs to be powered appropriately, you should assume that the output voltages will never be outside the range of ±10V. More than one op-amp might be required to complete some tasks. These must all be powered by named nets from the same pair of power supplies. For all circuits the positive power supply voltages should be named V1 and the negative supply named V2. They should be connected to the correct pins on the op-amps via named nets, named V+ (for the positive supply) and V- (for the negative supply). 1. Design an op-amp circuit that will take a voltage as an input and will amplify it with a gain of A. The input voltage source must be named V3. The named net for the input voltage should be Vin and named net for the output voltage must be Vout. [10 marks] 2. Design an op-amp circuit that will take a current as an input and will amplify it with a gain of B Q. You will need to add a current source to the circuit to demonstrate it working. The conventional current should flow towards ground from the current source. The current source should be labelled I1. The net for the output voltage must be labelled Vout. [10 marks] 3. Design an op-amp circuit that will take a voltage as an input and will amplify it with a gain of C. The magnitude of the current that flows through the feedback resistor must be between 0.1 mA and mA when the output from the amplifier is the maximum voltage possible (for your power supply voltages). The input voltage source must be named V3. The named net for the input voltage should be Vin and named net for the output voltage must be Vout. The feedback resistor must be named Rf. [20 marks] 4. Design a circuit that takes 3 voltages as inputs (a, b, and c) which has an output that is equal to D(Ea - Fb) + Gc. The three voltages sources used for the input voltages should be named VA, VB and VC and they should be connected to your circuit via named nets, named Va, Vb and Vc. [20 marks] 5. Create a voltage source labelled V3 and connect the positive terminal to a named net called Vin. Set a source resistance for the voltage source by right clicking on it and entering a value into the Series Resistance box. Voltage Source - V3 DC value [V]: Series Resistance [22]: 2000 OK Cancel Advanced X Figure 1: Setting the Series Resistance of V3 (for example to 2000 ohms). The value you use should be between 1000 and 10000 ohms. This setting will give the voltage source an output resistance. Looking from the point of view of an amplifer with an input of Vin, this is the also the source resistance. Design a circuit that will amplify the signal Vin with a gain of H dB. The gain of the circuit must not depend upon the value of Series Resistance chosen above. That is, if the Series Resistance is changed, the value of the output voltage should remain the same or almost identical. The named net for the input voltage should be Vin and named net for the output voltage must be Vout. Only use integer (whole number) values of Ohms for your resistances (round the value you require to 0 decimal places). [20 marks] 6. Design a circuit where the output voltage will be the difference between two input voltages, connected by named nets Va and Vb (the sources to be named VA and VB respectively), multiplied by J. The output, Vout, should be J (Vb - Va). The output should also be independent of the source resistances of the inputs (see Figure 1 for setting source resistances). It is also a requirement that the gain of the circuit be adjustable using only one resistor, which must be labelled Rg. The named net for the output voltage must be Vout. The common mode rejection ratio (CMRR) must be infinite. [20 marks]See Answer
Q9:Adjusting Transistor Length, Editing Models & Finding Small Signal Parameters. Unfortunately, when you change W and L in the PSPICE MOSFET Level 1 Model (the one we are using) it adjusts some but not all of the spice parameters in the correct manner. Changing W First and easiest to deal with is the area of the source and drain regions. The picture below shows a view of a MOSFET from above. AS is the area of the source and AD is the area of the drain in meters. In the PSPICE model AS and AD remain at their default value as the width is changed, which is incorrect. To fix this I revised the Capture Part to explicitly show AD and AS on the schematic. The areas given for the default 5 micron wide FETs now can be manually changed as you scale the width. For us Ldiff (E in the textbook) will be taken to be 1.5x10 meters (1.5 um) and to remain constant for all transistors. The areas will then be given by AS = AD=1.5x10 x W m². When changing transistor widths, you will need to compute these areas and enter them on the schematic to be passed to the SPICE model. These areas will not be affected by changing L. The good news is that these areas mainly influence the source-bulk and drain-bulk capacitances, they have no effect on currents. So unless you are doing a transient simulation, a frequency sweep or any in which these capacitances matter your answers will still be correct, but I would get in the habit of changing them anyway just so as not to forget, but you don't need to fiddle with them when you are trying to find the DC gain or set up bias conditions. NRS-N(source) PS= 2 x L (source) + W Lag (source) → AS-WXL (source) NRD=N(drain) PD=2x Lag (drain) + W Lag (drain) AD=WxLag (drain)/nThe situation is worse for adjustments to L, the good news is that often you will want to use the minimum length transistor as for the most part these give the best performance; highest speed, best gm for a given drain current etc. However sometimes like for current sources or cascoding transistors among other applications you would like to have transistors with a higher output resistance, ro. You can obtain a higher ro by increasing L. The problem here is that the built-in PSPICE MOSFET model we are using does not change the model parameter LAMBDA as it should. For these 0.5 um long device models Lambda is fixed at 0.1 irrespective of the gate length. It should scale like: where for the NFETs C=0.034 and for the PFETs C=0.064. Lambda=- с с Leff L-2LD These values for C are used so that we get the correct value of LAMBDA for the 0.5 μm long devices. Once you have the correct value of LAMBDA to use with the length that you have chosen you then need to edit the SPICE model for those devices which have the longer length. The next section will describe how to edit the SPICE model for individual transistors in your design. Note: If you want to change the ro of a transistor but not mess with its ID or VGs you can increase W by the same factor that you increased L. That keeps the W/L ratio constant and the ID current equation mostly unchanged. There is another wrinkle about which you should be aware. In saturation we use the formular, 1 AID 1+2 Vps. So, there will MID The MOSFET model equations implemented in PSPICE user= be a small disagreement for devices with a high VDs between hand calculations and SPICE unless you use the same formula that SPICE uses for your hand calculation. Model Editor The model editor is useful for more that just getting the effect of length changes correct. For instance, I used it to set GAMMA to zero in order to turn off the body effect for one of the homework solutions. To open the model editor select the transistor whose model you wish to change. Once selected, it changes color, then right click on the transistor. One of the options that show up in the context menu is "Edit PSPICE Model". Clicking on that opens the model editor. In the text box with the model parameters change the parameters that you wish to adjust. If you choose save then the model is saved in your local design library located in PSpice Resources>Model Libraries in your project Hierarchy on the first page of your project./nI change the model for every transistor that uses that original model in your design. To change the model for only the selected transistor you need to give it a new name. To do this change the name in the text box in the model editor before saving. Here is an example. The original model statement; .MODEL NFET4 NMOS would be edited for example to .MODEL NFET4-L10u NMOS. Now when saved the new model is still saved to your local design library but will apply to only the transistor that you originally clicked on and show up in the left panel of the Model editor with the new name. To use it elsewhere you can then just copy and paste the transistor on your schematic. This sometimes will not update the model name that appears on your schematic. To check which model a FET uses you can select and right click on a transistor and choose "Edit Properties". The Model name that will be used in the simulation is listed in the properties table next to "Implementation". This is all rather poorly documented in the PSPICE help files and manual so I hope that this is clear. Operating Point Here we will look at the effect of length changes on the output resistance of our NFET. Perform a bias point analysis for NFETs with gate lengths of 0,5, 1 and 2 microns. For the L=0.5 µm transistor use a width of 5 μm. Choose the widths of the other transistors so that all 3 transistors have the same W/L ratio. Bias their gates with 200 mV of overdrive and set the drain voltages to 3V. In the Simulation Settings be sure to check the "Include detailed bias point information for nonlinear controlled sources and semiconductors (OP)" option. This will save the small signal model for each transistor to the output file. Once the simulation runs view the Output file in the probe window. Toward the end you will see the list of your transistors and the small signal model parameters at the bias point for each. Copy this table into your report. It also lists the SPICE model parameters for each transistor, this is not what I want to see. Calculate the ro of each transistor to see the effect of the length change. I say calculate because SPICE does not report r, directly, rather it gives you the conductance between drain and source, GDS. In general, the bias point analysis is a good way to see what the small signal parameters are, especially for the parasitic capacitances which can be a bit tedious to calculate. It/non the schematic if you select the appropriate option buttons in the Capture toolbar. This analysis is most useful for setting up your desired bias points for designs. Sweep analysis of ro. Next for the same 3 transistors perform a DC Sweep analysis to generate the Ip vs VDS graph for each transistor. For ease of comparison graph them all on the same plot. Indicate the operating regions on your graph, any transition voltages and label each plot line with the transistor's gate length. Question: The VGs and W/L ratio is the same (or should be) for each transistor why do the curves look different? Explain. The slope of this graph at each point corresponds to the small signal drain-source conductance. Come up with a trace expression that will display to as a function of VDD. Plot ro for each transistor, all on the same plot. Note in particular what happens to ro when the devices enter triode. Often a graph like this will give you a better idea of what is going on than just looking at equations. Provide the equations for ro in each operating region and explain how they relate to your plot. Is your plot reasonable does it qualitatively agree with your plots? This last bit is sort of a check on your simulation, you always need to ask yourself if the SPICE results are reasonable, it is easy to make simulation errors. Provide: Source files PSICE Orcad 16.6 Simulation schematic for Bias point Operating Point Table Calculated Output resistances Simulation schematic for ID vs VDS plot, if different from that above. ID VS VDS Plot Question response To VS VDS plot. ro equations and comparisonSee Answer
Q10:6. Design a circuit where the output voltage will be the difference between two input voltages, connected by named nets Va and Vb (the sources to be named VA and VB respectively), multiplied by J. The output, Vout, should be J (Vb - Va). The output should also be independent of the source resistances of the inputs (see Figure 1 for setting source resistances). It is also a requirement that the gain of the circuit be adjustable using only one resistor, which must be labelled Rg. The named net for the output voltage must be Vout. The common mode rejection ratio (CMRR) must be infinite. [20 marks]See Answer
Q11:[20 mi 5. Create a voltage source labelled V3 and connect the positive terminal to a named net cal... Vin. Set a source resistance for the voltage source by right clicking on it and entering a value into the Series Resistance box. Voltage Source - V3 DC value[V]: Series Resistance[2]: 2000 X OK Cancel Advanced Comment Figure 1: Setting the Series Resistance of V3 (for example to 2000 ohms). The value you use should be between 1000 and 10000 ohms. This setting will give the voltage source an output resistance. Looking from the point of view of an amplifer with an input of Vin, this is the also the source resistance. Design a circuit that will amplify the signal Vin with a gain of H dB. The gain of the circuit must not depend upon the value of Series Resistance chosen above. That is, if the Series Resistance is changed, the value of the output voltage should remain the same or almost identical./nThe named net for the input voltage should be Vin and named net for the output voltage must be Vout. Only use integer (whole number) values of Ohms for your resistances (round the value you require to 0 decimal places). [20 marks]See Answer
Q12:4. Design a circuit that takes 3 voltages as inputs (a, b, and c) which has an output that is equal to D(Ea-Fb) + Gc. The three voltages sources used for the input voltages should be named VA, VB and VC and they should be connected to your circuit via named nets, named Va, Vb and Vc. [20 marks]See Answer
Q13:3. Design an op-amp circuit that will take a voltage as an input and will amplify it with a gain of C. The magnitude of the current that flows through the feedback resistor must be between 0.1 mA and 1 mA when the output from the amplifier is the maximum voltage possible (for your power supply voltages). The input voltage source must be named V3. The named net for the input voltage should be Vin and named net for the output voltage must be Vout. The feedback resistor must be named Rf. [20 marks]See Answer
Q14:1. Design an op-amp circuit that will take a voltage as an input and will amplify it with a gain of A. The input voltage source must be named V3. The named net for the input voltage should be Vin and named net for the output voltage must be Vout. [10 marks]See Answer
Q15:Give a tutorial (instructions of step by step for beginner of PSPICE Orcad 16.6), including screenshots and comments to produce the work of the tutor Suryadeep Mandal in order #266277.See Answer
Q16:6. In part 5, Provide LTspice simulation for all three parts of the above experiment. Compare the experimental and simulation results. This part hasSee Answer
Q17:2) Next generate a plot for Ip vs Vos for the diode connected NFET over 0-3 V of VDS bias. Include on your plot the effect of a bulk voltage of -0.5, 0, 0.5 and 1V. The easiest way to get all 3 curves on the same plot is to use 3 instances of the device in your simulation schematic, each with different bulk bias voltages. Using NET aliases can be useful here. Repeat for our PFET but now with bulk bias voltages of 3.5, 3, 2.5 and 2V. Here you should clearly see the body effect on the transistor characteristic. Replot these for the square root of ID vs VGs and estimate the effective threshold for each bulk voltage. For the NFET a) Schematic used for the simulation b) Plot showing the simulation results for ID vs VGs for the different bulk voltages. c) Plot of the square root of ID vs VGS for the different bulk voltages. d) A table showing the threshold voltages vs the bulk bias Then include the same for the PFET. (need the screenshots for these) General observations and suggestions: be sure you have a proper ground or the simulator will not work, it needs to be set as node zero. Setting the bias will be a challenge for many of you. Think about the meaning of the sign of the current. To make the PFET plots look "normal" you can change the signs of the voltages and currents plotted as appropriate. Use enough points in your simulation to make the curves look smooth. Note: clearly label the axes, label the traces with the Vgs or bulk bias voltages used, also make the traces thicker than the default and adjust colors for readability. Be careful in your choice of NFET3 or NFET4, only use the 3 terminal version if you are sure that the source voltage will always be at ground for the NFET. The NFET3 and PFET3 versions have their source and bulk terminals tied together internally. For our process this cannot be done for the NFET but it can for the PFET.See Answer
Q18:1) Generate the Ip vs Vps plots within the power supply limits of 0-3V, do this for gate- source voltages between zero and 3V spaced by 0.5 volts for both our default NFET and our PFET (W/L-5/0.5). This covers the full operating range of our devices. Label each trace with the VGs voltage used for each curve. For the NFET your plot should look qualitatively like this: 104 VGSI-VTH Saturation Region HLA-ESDA HLA-ESDA Vass Vosz Vast To do this you need to use a DC parameterized sweep with two loops, in one loop you are sweeping VDs and the other you are stepping VGs. To get the PFET characteristic to look like this you will need to change the signs of the some of the voltages and currents. b) Plots of the simulation results Repeat for the PFET Vos Careful: getting the PFET scans is trickier than you think, be sure that you cover the triode and saturation regions. (need the screenshots for these) Questions: For the NFET a) A legible copy of your simulation schematic, make sure it shows the device length and width a) For similar absolute values of the bias voltages the PFET and NFET drain currents are different, why? b) Observe how the slope of the curves in saturation change for different Vos. What does this imply about ro, the small signal output resistance as a function of Ves? c) What would the maximum current be if instead of a 5 micron wide device you had a 20 micron wide device?See Answer
Q19:300? Submit a table showing current gain, A = for B = 100, 200 and 300. What is the % variation in your gain across this range in ß (relative to B= 200, percent variation is calculated using (simulated-target x100%))? target H. SIMULATED INPUT RESISTANCE: Using the source amplitude found in part (F), what is the simulated input resistance, Rin, to your amplifier? Using current and voltage test probes at the amplifier input to calculate the input resistance using PSpice by placing cursors at the peak of each sinusoidal waveform and dividing the voltage result by the current. Note that the placement of V/I probes on the schematic in circuit areas where there is DC voltage and/or DC current will result in a DC offset in the simulated measurements, if so, either move the probe or subtract the DC offset from the results. Submit two plots showing the voltage and current waveforms used to calculate Rin having B= 200. Submit a table comparing your hand calculation and PSpice value for Rin. Submit a table showing PSpice values for Rin with B = 100, 200 and 300. I. SIMULATED OUTPUT RESISTANCE: What is the output resistance, Rout, to your amplifier? Replace the 64 ohm load with a voltage source at the output of your amplifier (leave the coupling capacitor between the source and the circuit). Remove the input voltage source and replace with a short (V-0). Using current and voltage test probes at the amplifier output, calculate the output resistance, Rout, using PSpice by placing cursors at the peak of each waveform and dividing the voltage result by the current. The voltage source should have a low amplitude to maintain a small signal condition. Submit the PSpice schematic of your test circuit. Submit a plot showing vo and io on two separate graphs for Bß = 200. Submit a table showing Rout for B = 100, 200 and 300. J. SIMULATION USING STANDARD RESISTOR VALUES: Using your PSPICE design, substitute standard resistors into your model by rounding up or down to the nearest values. The standard resistor values are listed in Appendix A noting there are two columns, one for 1/2 watt and one column for 3W. Match the resistance and associated power requirements to your design. SUBMIT the schematic with Standard Resistors. Using B=200, simulate the peak-peak current swing, small signal current gains and input resistance. Submit a table, comparing PSpice results for Vcc, Ico, VCEQ, PD. transistor with original resistors and the standard value resistors. K. Submit a plot showing it with clipping at both the positive and negative peaks using a B = 200. Submit plots of is and it under small signal conditions, calculate A₁. Submit plots of fin and Vin under small signal conditions, calculate Rin- Submit a table comparing the simulated peak swing, the simulated small signal gain and input resistance for your original design and the design with standard resistors. L. COMPONENT BILL OF MATERIALS (BOM) FOR LAB EXPERIMENT #3: Create the BOM, with standard resistor values (ohms), the quantities for each type of resistor and the required power spec (½ watt or 3 watt). Include the BOM in your project submission and also upload your BOM to Brightspace Assignments. Use the BOM form posted on Brightspace./nPART 2: PSPICE SIMULATIONS: A. SCHEMATIC: Submit your PSpice schematic clearly showing all values for DC voltage, DC current and DC Power for each element. All resistor values must clearly be shown on the schematic. B. SIMULATED DC BIAS: What are the simulated DC bias parameters, Ico, VCEO, VBEQ and transistor Power Dissipation, PD, transistor? Submit a table comparing your hand- calculated values to the simulated values for Ico, VCEO, VREQ, and PD, transistor. C. SIMULATED POWER SUPPLY BIAS: What is the total current delivered from the supply, Ips? Did you achieve the specification for maximum current? D. SIMULATED CURRENT SWING: Simulate your design in PSpice using a 1kHz sinusoidal input, use a voltage source with a 1K source resistor as shown above. Place a current probe on the wire leading into your circuit (on the left side of the capacitor). What is the largest peak-to-peak swing in the output current, it, through the 64 ohm load resistance? To find the maximum swing, you should slowly increase the source amplitude until the output current waveform begins to clip at the top or the bottom. Unless you have a design optimized for maximum symmetrical swing, it's most likely that the clipping will not be symmetrical. In other words, the point of clipping in the positive peak current will be different from the negative peak current. Submit a plot showing it with clipping using a ß = 200. When clipping occurs, chose the smaller of the two values and double this value, this is the peak-to-peak swing in the output current, i. Clearly report this peak-to- peak swing in the output current, iL. Did your design achieve the 100mA peak-to-peak swing? E. SIMULATED EFFICIENCY: Using the peak swing in load current, it (just below clipping), and load resistance, 64 ohms, calculate the simulated power conversion efficiency, n? You will need the total power supply current, Ips, from your simulation. Show all your calculations using data recorded from your simulated plots. Compare the hand-calculated value to the simulated value. F. SIMULATED SMALL SIGNAL OPERATION: Using PSpice, reduce the input source amplitude so that it is should be small enough to operate your transistor in the small signal region. Verify that the peak AC voltage across the Base-Emitter (B-E) junction, Vie, is less than 2.6mV peak (<<26mV). In OrCAD, you can verify the voltage using the "Differential Voltage Probe" measurement or just take the difference between two voltage probes placed at the base and the emitter. If he is greater than 2.6mV, decrease the source amplitude until the B-E voltage is in the small signal range. Record the amplitude value of the source voltage for small signal operation. Submit a plot showing of the for B= 200. G. SIMULATED GAIN: Using the input source with amplitude set to the value found in part (F), what is the small signal gain, A = at B= 200? Submit two plots showing is and iL under small signal conditions using a ß = 200. Edit the transistor model and change the value for 3 to 100 and then to 300, record the small signal gain for each condition. What is the variation in the current gain, A₁ = when ẞ is varied over the range from 100 to Rev 0.0/nIm • • 1 ΚΩ Design Notes: • in Rin [ C₁ Vcc Ips Your Amplifier Design 1 64 02 V Rout C₂ out value in CircuitLab, select 2N2222 and change "B_F" to the value To change the required. To change the value in OrCAD, select Q2N2222 in "Eval" library and right mouse click on transistor to edit the "PSpice Model". Change the value for fr. Resistors can have any value at this point in the design. You don't need to adhere to industry standard values unless you want to (could be helpful later). If you calculate a resistor of 2 ohms or less, then you probably don't need this one. • When calculating the DC operation of your circuit, it could be helpful to use VBEQ = 0.8V. At the higher ICQ values, the B-E voltage increases beyond 0.7V. • There will be differences between your hand calculations and the PSpice results. Enter you hand-calculated design into PSpice and slightly adjust the resistor(s) until you achieve the required specifications in PSpice. When performing a transient analysis, it is best to set "maximum step size" to 0.01 msec and simulate over a range of 3 msec. PART 1: HAND CALCULATIONS A. Submit all hand calculations for your design. It is important to show how you decided on your resistor values and operating conditions. B. What is your calculated power conversion efficiency, ? Show all the steps for this calculation. C. Draw (by hand) your complete schematic with the final resistor values. D. Draw a plot of the AC and DC load lines on the same ic versus VCE graph. Clearly show the x- and y-intercepts, with values, for each. Clearly label the Q point. Load line calculations can assume that = infinite (a = 1). E. In a table, list your DC bias parameters; Vcc, Ico, VCEQ, PD, transistor? F. In a table, and for a value of ß = 200, list your calculated small signal current gain, Ai, Input Resistance, Rin, and Output Resistance, Rout G. What is your maximum peak-to-peak current at the load? Show the calculation.See Answer
Q20:Task 2: Single-phase half-wave phase-controlled rectifier with RL load Recall Chapter 2, Make a new project. Build a single-phase half-wave phase-controlled rectifier with RL load Use the sinusoidal source in the SOURCE lib set amplitude 450V and frequency 20Hz Use the pulse voltage source in the PSpice Component and set the rising time lus, falling time /us, pulse width 100μs, low-side output voltage OV, and high-side output voltage 201 Use the load parts in the PSpice Component set resistor 50, and inductor 20mH in series. Use the thyristor in the ELEC4174_Fall_2023 library. Use the time domain simulation set up, set run to time as 50ms and maximum step size as le a. Show your schematic. b. If we have voltage pulse (gate signal) appears at 15ms, 1) Plot the voltage across the resistor and voltage across the inductor. 2) Find the conduction angle (approximately) using results in part b.1). 3) Evaluate your plots in part b.1) for maximum value for VR and the point when V₁ across 0, briefly explain with words or equations what happened there.See Answer

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