1) Generate the Ip vs Vps plots within the power supply limits of 0-3V, do this for gate- source voltages between zero and 3V spaced by 0.5 volts for both our

default NFET and our PFET (W/L-5/0.5). This covers the full operating range of our devices. Label each trace with the VGs voltage used for each curve. For the NFET your plot should look qualitatively like this: 104 VGSI-VTH Saturation Region HLA-ESDA HLA-ESDA Vass Vosz Vast To do this you need to use a DC parameterized sweep with two loops, in one loop you are sweeping VDs and the other you are stepping VGs. To get the PFET characteristic to look like this you will need to change the signs of the some of the voltages and currents. b) Plots of the simulation results Repeat for the PFET Vos Careful: getting the PFET scans is trickier than you think, be sure that you cover the triode and saturation regions. (need the screenshots for these) Questions: For the NFET a) A legible copy of your simulation schematic, make sure it shows the device length and width a) For similar absolute values of the bias voltages the PFET and NFET drain currents are different, why? b) Observe how the slope of the curves in saturation change for different Vos. What does this imply about ro, the small signal output resistance as a function of Ves? c) What would the maximum current be if instead of a 5 micron wide device you had a 20 micron wide device?