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Challenges Where Students Need Logisim Assignment HelpLogisim assignments present students with a unique set of challenges that can be demanding to overcome. Here, we'll delve into these specific challenges that students face while solving Logisim homework tasks:
1. Complex Digital Circuit Concepts
Logisim assignments delve into complex concepts related to digital circuit design and analysis. These concepts can be overwhelming, particularly for students in the early stages of their digital electronics studies.
2. Unclear Instructions
Some students receive unclear or insufficient instructions for their Logisim assignments from their professors or educational institutions. This lack of clarity can make students uncertain about how to tackle their assignments.
3. Practical Circuit Design
Logisim assignments require students to design digital circuits practically. Students will struggle with circuit layout, simulation, and validation, which can impact the quality of their assignments.
4. Simulation and Testing
Logisim assignments involve simulating digital circuits and testing their functionality. Students may face difficulties in accurately simulating circuits and interpreting simulation results.
5. Optimizing Circuit Efficiency
Creating circuits that are both functional and efficient in terms of component usage can be challenging, requiring students to explore different design techniques.
Logisim Topics & Concepts Covered
| Topics | Concepts |
|---|---|
| Combinational Logic | Multiplexers, Demultiplexers |
| Sequential Logic | Registers, Counters |
| Arithmetic Circuits | Adders, Subtractors, Multipliers |
| Memory Units | SRAM, DRAM, ROM, RAM |
| Multiplexers & Decoders | Priority encoders, Multiplexers |
| Clocking & Timing | Clock signals, Clock generation |
| Custom Components | Designing custom logic components |
| Simulation | Running simulations, testing circuits |
| Wiring and Connections | Connecting components, wires, buses |
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Recently Asked Logisim Questions
Expert help when you need it- Q1:Your task is to construct an encoder circuit that has 4 inputs (A, B, C, and D) representing a binary number from 0 to 9, and has 7 outputs representing the segments in a seven-segment display. You will connect the circuit in Logisim and test it with the built-in 7-Segment-Display component in Logisim.See Answer
- Q2:ALU Implementation 1 INTRODUCTION We have learnt in "Platforms for Computing" module about different levels of computing platforms. An example machine that we dealt with is the CdM-8 machine. As we know, the CdM-8 machine is composed of several units that include arithmetic and logic unit (ALU), Registers, etc. In this task we will explore how to create an ALU that can perform different operations. 2 YOUR TASK You need to use Logisim software to design a simple 4-bit ALU that can perform different types of operations on 4-bit numbers. The ALU should accept two 4-bit inputs, and a 2-bit opcode that determines the required operation. Finally, after performing the requested operation, a 4-bit result, and CVZN flags are generated. The ALU operation is selected based on the opcode input of the instruction. The opcodes and the operations that can be performed are described in table1 below, assuming that the two 4-bit inputs to the ALU are named A and B: Table 1 The operations supported by ALU Opcode (2-bit) Operation A + B A-B A++ A == B (Check equality, result should be 0 or 1) 00 01 10 11 The result and the flags should be generated correctly according to the requested operation. 3 TESTING YOUR CIRCUIT You should test your circuit thoroughly before submission. You will be penalized for any missing, incomplete, or incorrect operation. 4 SUBMISSION REQUIREMENTS: You should submit two files a report, and a circuit file. Report: is a word or a pdf document that talks about the development of your project and the steps you followed to produce the required circuits. It should contain at least 4 sections: introduction, design, testing & results, and conclusions. Circuit: is a single Logisim file that contains your actual implementation of the project. each component in the project should be represented in this file as subcircuit (as shown in Lectures and tutorials). Page 1 of 1See Answer
- Q3:ELEC2042 Minor Project Three Floor Lift We have seen a lift that moves between two floors in lectures. We will now extend this to three floors. Your lift, and the state machine, will start on floor zero. The 10 available flip flops will all be reset to zero on start. When a floor button is pressed the corresponding input changes to 1. When the button is released the corresponding input will change back to 0. When a floor is signalled your lift should start to move to that floor. As the lift moves if the button for the current floor has been pressed then the lift should stop at that floor. Your lift should implement an elevator algorithm, that means that it continues moving in the current direction until it reaches the last floor requested in that direction. It should not reverse direction without stopping at all floors (either up or down) that were requested. In a practical sense it means if the lift is currently at floor 0 and buttons 1 and 2 are pressed it will start to move upwards. If when moving, but before floor 1 is reached, button 0 is pressed the lift should only move back towards floor 0 after floor 2 has been reached. The lift optionally has doors. This is signified by setting the Has_Doors output to 1. If set to 1 this output must remain as 1, it is a fault if this output changes from 1 to 0. Your lift controller can request the doors be opened by setting the Open/Close output to 1. When that output is 0 the doors will close. The Door_State input will identify the current state of the doors. ELECTRICAL 1 of 4 Three Floor Lift Minor Project v1/nYou are to produce a PDF document that describes your project, and the equations that will implement your lift controller. The PDF document details each of the following elements: 1 A high level summary of your design. In this summary you will describe the thinking that was behind your design, and why you have the elements you do in your design. This design is a conceptual description of your solution. You will need to create a Moore design for your system. 2. The state transition diagram. This will hold each state the system is in, and what causes a transition between those states. 3. Details of the memory elements utilised in your design, as well as the different combinatorial circuits. • It is possible, and required, that this design can be accomplished with less than 11 D flip flops as the memory elements. These can be called: DO, D1, D2, up to D9as the D inputs to each, and Qo, Q1, Q2, up to Q9as the outputs of each D flip flop. 4. A state transition table detailing the inputs and outputs of the combinatorial circuit components. • The inputs will be Floor_0, Floor_1, Floor 2, Button_0, Button_1, Button_2, Door_State as well as the current state Qs (Q0, Q1, Q2... Q9). • The outputs will be D0, D1, D2... D9 (the next state), Has_Doors, Open/Close, Up/Down, as well as Move/Stop. 5. Karnaugh Maps for your combinatorial circuits. • You will need to use a don't care techniques to simplify the Karnaugh maps so they can be completed by hand. 6. Minimal Sum of Products equations for your Kamaugh Maps. • For the minimum SoPs you will also enter these in a special submission box which will be automatically graded. The equations for the Minimal Sum of Products will be entered into a quiz on iLeam. These equations will be graded using a lift simulator to ensure your lift operates correctly. The functioning of your lift will dictate the grade level of your assignment. ELECTRICAL 2 of 4 Three Floor Lift Minor Project v1/nThe Inputs, and their means are detailed below: Input Floor_0 Floor 1 Floor_2 Button 0 Button_1 Button_2 Door_State[0:1] The Outputs, and their required meanings are detailed below: Meaning The lift will move when 1, or be stationary when 0 The lift motor should move up when 1, or down when 0 The doors should open when 1, and close when 0 When 1 the lift has doors, when 0 door inputs and outputs are ignored Output Move/Stop Up/Down Open/Close Has_Doors Meaning (When 1) The lift is registered as present at floor 0 The lift is registered as present at floor 1 The lift is registered as present at floor 2 The request button has been pressed for floor 0 The request button has been pressed for floor 1 The request button has been pressed for floor 2 The doors are closed [00], opening[01], open [11] and closing[10] ELECTRICAL 3 of 4 Three Floor Lift Minor Project v1/nGrading will consist of a series of tests on the equations. The document may be examined for additional detail if questions arise from the running of the equations. Your equations will be run in a simulator and your lift will be given a set of inputs. The outputs will be examined to verify the lift performs as it is supposed to perform. For a HD grade the door functions must be implemented. However, if your code asserts Has_Doors, and the doors don't function then the highest grade you can obtain will be credit. You will be awarded the LOWEST grade for which you qualify: Grade Fail Pass Credit Minimal Solution with all elements of the document present, some problems with overview of the solution, incorrect justification of the solution chosen, SoP are not minimal, Lift equations move between all three floors in perfect cases, but some errors in other test cases. Asserts Has_Doors and doors do not fully function. Distinction Solution that works and adequate justification, mapping between state diagram and state transition table is unclear. The lift passes all non-door tests and does not pass all door tests. Reasons for awarding this grade (OR list) No submission, submission is not readable, submission does not answer the criteria. Minimal Solution, some faults are present, some elements of the solution are missing, Karnaugh Maps are not present. High Distinction Solution that works with a complete and detailed justification and all elements required are complete. The lift functions and doors open/close. Also, the machine tests all pass. ELECTRICAL 4 of 4 Three Floor Lift Minor Project v1See Answer
- Q4:This homework requires you to design and implement the Duke 250/16, a 16-bit MIPS-like, word- addressed (not byte-addressed) RISC architecture. (A word is 16-bits.) We have specified the architecture, and you will use Logisim to design a single cycle implementation of this architecture. The architecture's instructions are specified in Table 1. Submission instructions - please read VERY carefully: You must do all work individually, and you must submit your work electronically via GradeScope. • You will submit a Logisim file called cpu.circ. This file is the circuit for your processor. . ● If your CPU is failing one or more tests, you are encouraged to submit a PDF file called cpu.pdf. This file is your description of your processor, and the grading TA will use this description to help assign partial credit. (This file is for your benefit!) The file should explain the following issues: o What parts of your processor work and which parts do not work. This helps us to find partial credit. o For subcircuits (e.g., register file or ALU), explain their interfaces so that we can possibly test them individually. • Non-functioning CPUs will receive partial credit of 10 points plus incremental credit for functioning subcircuits (up to 70 points); this credit will be guided by your cpu.pdf write-up. • All submitted circuits will be tested for suspicious similarities to other circuits, and the test will uncover cheating, even if it is "hidden." Plagiarism of Logisim code will be treated as academic misconduct. • Logisim implementations must use only the components specified in the "Logisim restrictions" section later in this document. For successful automated grading, your circuit must meet the requirements specified in the "Automated testing" section. • You may not use any pre-existing Logisim circuits (i.e., that you could possibly find by searching the internet).See Answer
- Q5: Problem: Explain the operation of the D flip-flop. Design and implement a D flip-flop bidirectional counter which produces the following repeated binary sequence: 0, 7, 1, 6, 2, 5. Note: Design the final circuit in Logisim software.See Answer
- Q6:2 Seven Segment Decoder (5 points) A seven segment decoder is typically used to determine which light emitting diodes in a seven segment display should illuminate to display a digit specified in binary coded decimal. Logisim includes such a seven segment display that you will use in this question. The decoder takes as input four binary bits, which we label in order from most significant bit to least significant bit, A3 A2 A1 A0. The decoder produces as output a pattern of 7 bits, S6 S5 S4 S3 S2 S1 S0, which specifies which seg- ments should illuminate. The figure on the right shows the relationship between the pins and the corresponding segments of the display. Note that there is an 8th pin, S7, which controls the decimal point and that we will not use in this assignment. In this question, Instead of decoding BCD, your decoder should produce your BID for binary bit patterns 0 through 8. (For example, if the input is 0, dis- play the first digit of your ID. If the input is 1, diplay the second digit of your ID.) You can produce any output (i.e., we don't care) for inputs of binary bit patterns 9 through 15. If your ID is 0123456789, your decoder should produce exactly the patterns shown below. exactly the patterns shown below. 0323956789 SO S1 S2 S3 S1 S4 S2 50 S3 56 S5 S7 S4 S5 S6 S7 1. Write out a truth table for your circuit and include this with your written answers. 2. Implement the 7 boolean functions in the provided logisim circuit file using only AND, OR and NOT gates provided in the built in library (it is also OK to use NAND and NOR gates, and to negate inputs on gates). You may use any solution you wish, but you may find it easiest to use a sum of products approach, much like a PLA. Create your solution in the provided circuit file, as it already has a set of inputs and outputs defined. These input and output pins should not be moved so as to prevent the sub-circuit appearance from changing (right-most tool bar button in logisim) as this is important for testing.See Answer
- Q7:Lab 01 Q1 Introduction 30 Points Logisim-Evolution is used to create and test simulations of digital circuits. This part of the lab is designed to introduce Logisim-Evolution and teach the fundamentals of using this application. The purpose of this part of the lab is to install and test the Logisim-evolution system and become comfortable creating a digital logic circuit. To receive a grade for this part of the lab, create the Simple Multiplexer as defined in this lab, be sure the standard identifying information at the top left of the circuit Name: Joe Bloggs Username: jbologgs01 Introductory Exercise February 18, 2020 and then save the file with this name: Lab01_Mux21.circ (that stands for multiplexer, 2-way, 1-bit). Submit that circuit file for grading. Please select file(s) Select file(s)See Answer
- Q8:Propiem Statement. This report is based on the last Digital Electronics laboratory session. You need to go through the steps and complete the given tasks. Here is a summary of the lab and tasks you need to do. In this exercise we want to simulate a simple 4-bit programmable computer system. Our computer is capable of toggling 4 relay switches on and off based on the given program. The program is stored in a 256x4 ROM component. Each 4-bit cell represents a line of code. The first bit sets the status of the relay (on = 1, off=0). The second bit is not used (can be ignored). The last two bits are the address of the relay (00 = relay 1, 01 = relay 2, 10 = relay 3, 11 = relay 4). The computer operation starts by reading the ROM content at address 0 (reading cycle). The ROM outputs are interpreted and set the corresponding relays (processing cycle). With each clock cycle, the ROM address increases, and the new settings are applied to the relays. After each clock cycle the command is read from ROM an interpreted by the processing unit. The processing unit (ALU) sets the designated relay status based on the contents of the ROM. These cycles continue till the computer reaches the end of the program which is identified by a stop point. After reaching the end of the code, the address is set to zero and the whole process repeats. The user can set the stop point of the program using 8-bit dip switches. The computer can be reset by a reset switch which restart the reading/processing cycles from address 0. The computer can be stopped and run by a toggle switch (start/stop). Objectives: 1- Create the system block diagram representing the computer with main required block (10%) 2- Add a description on how your solution works and explain the purpose of each block in your diagram (10%) 3- Create the computer circuit schematic in the simulation software: a. Add correct gates and other required logic components and connect them (30%) b. Add comment to your simulation file (5%) c. Use a hierarchy to break down the system into smaller modules (5%) 4- Perform the simulation and show the functionality of the computer by plotting the correct timing diagram: a. Show the reading and processing cycles as well as relay states for at least one memory address (10%) b. Show the function of reset button (10%) c. Show the function of start/stop button (10%) d. Show the function of start/stop point (10%) The report needs to be submitted as a PDF file with each section clearly specified using the numbers given in the objective section./nLearning Outcomes: Knowledge and Understanding: 1. Knowledge of mathematics will be applied to analyse communication systems and digital circuits, will be assessed in the coursework. (AHEP4, C1) Intellectual Professional skills & abilities: 3. Design methodology will be covered, starting from a set of specifications and design of digital and communication systems. This will be assessed in the coursework. (AHEP4, C5) 1 4. A set of 4 experiments in the semester will allow the students to develop their practical skills. Will be assessed in the coursework. (AHEP4, C12, M12)See Answer
- Q9: AM M Assignment KD4009 (Component 002 - Lab Report) 2023/24 Module Information Module Title: Digital Electronics and Communications Module Code: KD4009 Module Tutor: Mojtaba Mansour Abadi Assessment set by: Mojtaba Mansour Abadi Academic Year: 2023-2024 Northumbria University NEWCASTLE Dates and Mechanisms for Assessment Submission and Feedback Date of hand out to students: 02/10/2023 Mechanism to be used to disseminate to students: eLP Date and Time of Submission by Student: 22/01/2024 Mechanism for Submission of Work by Student: eLP Date by which Work, Feedback and Marks will be returned to Students: 02/02/2024 Mechanism(s) for return of assignment work, feedback and marks to students: eLP Assignment Brief Clear statement of the work that students are expected to undertake: Please see the instruction below Further Information Learning Outcomes assessed in this assessment: Assessment Criteria/Mark Scheme: See the guidance below Referencing Style: References are included in IEEE style Expected size of the submission: The report should not exceed 25 pages including all figures and code Assignment weighting: This assignment is worth 40% of the module marks. It is an individual assignment. Academic Integrity Statement: You must adhere to the university regulations on academic conduct. Formal inquiry proceedings will be instigated if there is any suspicion of plagiarism or any other form of misconduct in your work. Refer to the University's Assessment Regulations for Northumbria Awards if you are unclear as to the meaning of these terms. The latest copy is available on the University website. Failure to submit: This coursework is compulsory. The University requires all students to submit assessed coursework by the deadline stated in the assessment brief. Where coursework is submitted without approval after the published hand-in deadline, penalties will be applied as defined in the University of Work. Late Submission Policy on the https://www.northumbria.ac.uk/static/5007/arpdf/lateappr Learning Outcomes: Knowledge and Understanding: 1. Knowledge of mathematics will be applied to analyse communication systems and digital circuits, coursework. (AHEP4, C1) will be assessed in the Intellectual Professional skills & abilities: 3. Design methodology will be covered, starting from a set of specifications and design of digital and communication systems. This will be assessed in the coursework. (AHEP4, C5) 1 4. A set of 4 experiments in the semester will allow the students to develop their practical skills. Will be assessed in the coursework. (AHEP4, C12, M12) 4-bit computer (L1, L3, L4) Problem Statement: This report is based on the last Digital Electronics laboratory session. You need to go through the steps and complete the given tasks. Here is a summary of the lab and tasks you need to do. In this exercise we want to simulate a simple 4-bit programmable computer system. Our computer is capable of toggling 4 relay switches on and off based on the given program. The program is stored in a 256x4 ROM component. Each 4-bit cell represents a line of code. The first bit sets the status of the relay (on = 1, off = 0). The second bit is not used (can be ignored). The last two bits are the address of the relay (00 = relay 1, 01 = relay 2, 10 = relay 3, 11 relay 4). = The computer operation starts by reading the ROM content at address 0 (reading cycle). The ROM outputs are interpreted and set the corresponding relays (processing cycle). With each clock cycle, the ROM address increases, and the new settings are applied to the relays. After each clock cycle the command is read from ROM an interpreted by the processing unit. The processing unit (ALU) sets the designated relay status based on the contents of the ROM. These cycles continue till the computer reaches the end of the program which is identified by a stop point. After reaching the end of the code, the address is set to zero and the whole process repeats. The user can set the stop point of the program using 8-bit dip switches. The computer can be reset by a reset switch which restart the reading/processing cycles from address 0. The computer can be stopped and run by a toggle switch (start/stop). Objectives: 1- Create the system block diagram representing the computer with main required block (10%) 2- Add a description on how your solution works and explain the purpose of each block in your diagram (10%) 3- Create the computer circuit schematic in the simulation software: a. Add correct gates and other required logic components and connect them (30%) b. Add comment to your simulation file (5%) c. Use a hierarchy to break down the system into smaller modules (5%) 4- Perform the simulation and show the functionality of the computer by plotting the correct timing diagram: a. Show the reading and processing cycles as well as relay states for at least one memory address (10%) b. Show the function of reset button (10%) c. Show the function of start/stop button (10%) d. Show the function of start/stop point (10%) The report needs to be submitted as a PDF file with each section clearly specified using the numbers given in the objective section.See Answer
- Q10: Fatemah Ameen 45803 Sara h Alenezi Nour 58487 Noor Al Deen - 50388 CPEG 210 - Digital Logic Design Fall 2023 Project Important Information & Instructions 1. The weight of this project is 15% 2. Students should work on this project in teams (3 or 4 members per group). 3. Only one member of the team should submit the project via Moodle the following two files: a. The digital circuit diagram of the solution along with any discussions and truth table(s) as a single PDF file. b. Your Logisim .circ file. 4. The deadline to submit your files is January 04, 2023 by 11:59 pm. Project Description and Requirements Consider a digital circuit that has three inputs A, B, and C and four outputs X, Y, Z and F (Flag). Let A, B, and C be the unsigned binary representation of the number W where W can take values from 0 to 7. If W is in the range between 0 and 4, then the outputs X, Y, and Z should be the unsigned binary representation of (W+3) and the Flag (F) must be 0. For example, if W=2 then A B C = 010, and therefore the outputs X Y Z should be 101 (equivalent to 5) and F must be 0 and so on. If W is equal to 5, 6, or 7, the outputs X Y Z must be 000 and the Flag (F) must be 1. Design a digital circuit using a minimum number of components from the following list: • Decoders • Encoders • • Multiplexers Logic gates (AND, NAND, OR, NOR, XOR, NOT gates). If your solution doesn't use the minimum number of components/gates but produces correct results, you will lose 1/3 of the total mark (i.e., 5 points deduction) A σ 0 O о B C о 0 x Y 1 N F 1 Do DI D₂ 8:3 D3 Do Encoder Y Dy b₁ Ds Da 3:8 D3 B D6 Da Z D4 Decoder Ds C 06 OR F 07See Answer
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