Fatemah Ameen 45803 Sara h Alenezi Nour 58487 Noor Al Deen - 50388 CPEG 210 - Digital Logic Design Fall 2023 Project Important Information & Instructions 1. The weight of this project is 15% 2. Students should work on this project in teams (3 or 4 members per group). 3. Only one member of the team should submit the project via Moodle the following two files: a. The digital circuit diagram of the solution along with any discussions and truth table(s) as a single PDF file. b. Your Logisim .circ file. 4. The deadline to submit your files is January 04, 2023 by 11:59 pm. Project Description and Requirements Consider a digital circuit that has three inputs A, B, and C and four outputs X, Y, Z and F (Flag). Let A, B, and C be the unsigned binary representation of the number W where W can take values from 0 to 7. If W is in the range between 0 and 4, then the outputs X, Y, and Z should be the unsigned binary representation of (W+3) and the Flag (F) must be 0. For example, if W=2 then A B C = 010, and therefore the outputs X Y Z should be 101 (equivalent to 5) and F must be 0 and so on. If W is equal to 5, 6, or 7, the outputs X Y Z must be 000 and the Flag (F) must be 1. Design a digital circuit using a minimum number of components from the following list: • Decoders • Encoders • • Multiplexers Logic gates (AND, NAND, OR, NOR, XOR, NOT gates). If your solution doesn't use the minimum number of components/gates but produces correct results, you will lose 1/3 of the total mark (i.e., 5 points deduction) A σ 0 O о B C о 0 x Y 1 N F 1 Do DI D₂ 8:3 D3 Do Encoder Y Dy b₁ Ds Da 3:8 D3 B D6 Da Z D4 Decoder Ds C 06 OR F 07