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Q1:pset3-2024-spring_58_1717053712071.ipynb - Colab 30/05/2024, 13:55 v Spring 2024 ECE M16: PSET 3 (ver. 1.1) Student Name: LEONARD, MICHAEL Instructions (Please read !!! ): 1. This notebook is personalized for you. Make sure you have downloaded the notebook that was listed against your name. 2. Deadline to submit is as listed on Gradescope. 3. You can make three submission attempts. We do not count submissions detected to have tampered with notebook cells that prevent grading (e.g. if there are more or fewer cells than expected or there is a match of cell type). For the first attempt, the Autograder will only perform some basic sanity checks on the basic format of your answer and return a score of 0. It will, however, not check or provide feedback on the correctness of your answer. For example, if the answer has to be a list of base-10 integers, then the sanity check will check whether you indeed provided10 a list of base-10 integers. Likewise, if the answer asks for a logic expression, the sanity check will check whether your answer is indeed a valid logic expression (however, it will not check whether the variable names used are correct). For the second and third attempts, the Autograder will also report whether your answer is correct or not, but it will not tell you what the correct answer is or why your answer is wrong. 4. If we discover a bug in the Autograder, we will compensate the impacted students with an extra attempt only for the impacted question. For other questions unaffected by the bug, the score the end of third attempt will be used. 5. Please do not edit, move, or delete any of the cells. You must only write in the cells provided for your answers while adhering strictly to the format requirements. Otherwise, the Autograder cannot grade, and even though we do not count the attempt, it will cause you needless panic. 6. Most problems/subproblems will be auto-graded, and it is critically important that you strictly adhere to the formatting requirements for the answers. A few will be graded manually, and there you are allowed free-form text, either plain text or in Markdown format. 7. After every problem or subproblem, we have provided a cell where you can optionally provide a brief explanation of your solution approach. By default, we will not grade the explanation but use it if your answer is marked wrong by the autograder or the human grader, and you request a regrade. No regrade request will be entertained unless an explanation of how you derived your answer is provided. The explanation cells can accept text in Markdown format. https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 1/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab v Problem 1: Sequential System Analysis [10.0 points] Consider the following sequential circuit and answer the questions in the parts that follow. When answering, use standard boolean logic operators ~, &, |, ^, and parentheses. SO TSQ 0 . 0 b Z R . S1 TSQ O sysclk b R p (Note: if an image doesn't show up above, please click on this link). v Part 1.1: SOnext [1.5 points] Write the boolean logic expression for S0next in terms of S0 and S1 . Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 1.2: S1next [1.5 points] Write the boolean logic expression for S1next in terms of S0 and S1 . Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 2/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab v Part 1.3: Z [1 points] Write the boolean logic expression for Z in terms of S0 and S1 . Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 1.4: Isolated States [1.5 points] An isolated state is a state with the property that if the system starts in that state on power up, it stays there forever. Consider which of the following statements are true. 1. S0=0, S1=0 is an isolated state 2. S0=1, S1=0 is an isolated state 3. S0=1, S1=1 is an isolated state 4. S0=0, S1=1 is an isolated state 5. This system does not have an isolated state Your answer should be a list of decimal integers corresponding to the true choices. The list must not include any incorrect choices. The list may be empty (write it as []), have only one element (e.g., [1]), or may have multiple elements (e.g., [1,2,3]). Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 1.5: Temporal Evolution of Z [4.5 points] Let the system clock sysclk have a frequency of 500 MHz, and assume that at time t = 0 we had a rising edge of the clock and that both the state bits S0 and S1 were 0. What will be the value of Z at t = 2 ns, 4 ns, 6 ns, and 8 ns respectively? Your answer should be a comma- separated list with four elements, each of which is 0 or 1 or X (unknown), and with the first element in the list corresponding to Z at t = 2 ns, the second to to Z at t = 4 ns, and so on. E.g., https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 3/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab your answer may be [0,0,1,1] to indicate the Z=0 at t = 2 ns and 4 ns, and Z=1 at t = 6 ns and 8 ns. Note: You must get all time instant correct in order to get credit. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Problem 2: Improving System Performance [15.0 points] In all the sub-questions below, assume that the registers being used have setup time ts = 11 ps, hold time th = 9 ps, propagation delay tacQ = 11 ps, and no clock skew. Note thast ps means picoseconds and equals 10-12 s, and GOPS means billion operations per second and equals 109 operations/second. v Part 2.1: Baseline Throughput [2.5 points] Consider the datapath below and assume that the combination logic has a propagation delay 319 ps. R X Combinational Logic E - Z G G A CLK CLK (Note: if an image doesn't show up above, please click on this link). What is the maximum throughput of this system, i.e. the rate at which it can process data at input X? Your answer should be a real number in units of GOPS (Giga Operations per Second). Do not include units. Your answer should be accurate to three digits after the decimal point. E.g., you answer could be 15.231. Enter_your_answer_in_required_format https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 4/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab Optional Explanation: Replace this text with your explanation. v Part 2.2: Baseline Latency [2.5 points] Continuining with the preceding, what is the input to output latency? Specifically, we are looking for the delay between when an instance of a value of X was stored at a clock edge in the input register (on the left) and the value obtained after processing it gets stored at a later clock edge in the output register (on the right)? Your answer should be a number in ps. Do not include units. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 2.3: Throughput with Uniform Pipeline Stages [2.5 points] Now say we divide the combinational logic into three equal stages, each of which has a propagation delay of 319/3 ps. R × Combinational Logic Combinational Logic Combinational Logic E - Z G G 1 A < < CLK CLK CLK CLK (Note: if an image doesn't show up above, please click on this link). What is the maximum throughput of this system, i.e. the rate at which it can process data at input X? Your answer should be a real number in units of GOPS (Giga Operations per Second). Do not include units. Your answer should be accurate to three digits after the decimal point. E.g., you answer could be 15.231. Enter_your_answer_in_required_format Optional Explanation: https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 5/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab Replace this text with your explanation. v Part 2.4: Latency with Uniform Pipeline Stages [2.5 points] Continuining with the preceding, what is the input to output latency? Specifically, we are looking for the delay between when an instance of a value of X was stored at a clock edge in the input register (on the left) and the value obtained after processing it gets stored at a later clock edge in the output register (on the right)? Your answer should be a number in ps. Do not include units. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. Part 2.5: Throughput with Non-uniform Pipeline Stages [2.5 points] Consider the the datapath below where there is a sequence of six combinational blocks, named A, B, C, D, E, and F, with propagation delays of Now suppose that the original combinational block is divided instead into a sequence of six blocks, named A, B, C, D, E, and F, with propagation delays of 80 ps, 30 ps, 60 ps,50 ps, 70 ps, and 10 ps respectively, as shown the figure below. R X - E - A - B C - D E + F - E · Z G G A 1 CLK CLK (Note: if an image doesn't show up above, please click on this link). You are given two pipeline registers, and you seek maximum throughput. What throughput can you achieve (in GOPS, without units)? Your answer should be a real number in units of GOPS (Giga Operations per Second). Do not include units. Your answer should be accurate to three digits after the decimal point. E.g., you answer could be 15.231. Enter_your_answer_in_required_format https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 6/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab Optional Explanation: Replace this text with your explanation. v Part 2.6: Latency with Non-iniform Pipeline Stages [2.5 points] Continuining with the preceding, what is the input to output latency? Specifically, we are looking for the delay between when an instance of a value of X was stored at a clock edge in the input register (on the left) and the value obtained after processing it gets stored at a later clock edge in the output register (on the right)? Your answer should be a number in ps. Do not include units. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. Problem 3: Sequential Systems Fundamentals [10.0 points] v Part 3.1: States with JKFF? [2.5 points] What is the maximum number of states a circuit with n JK flip-flops can be in? Select the correct option from the list below. 1. None of the other choices 2. n2 3.2n 4. 22n 5.27 6. n Your answer should be a base-10 integer corresponding to the correct option. Enter_your_answer_in_required_format Optional Explanation: https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 7/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab Replace this text with your explanation. v Part 3.2: Chained FSMs [2.5 points] Consider a digital system S composed of 4 interconnected sequential logic subsystems A, B, C, and D which have {{4, 6, 3, and 7 states respectively. What is the maximum number of possible states in the system S? Your answer should be a base-10 integer. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 3.3: Chained FSMs (contd.) [2.5 points] Assuming A, B, C, and D in the preceding part are all implemented separately using JK Flipflop (JKFF), at least how many JKFFs are needed to implement S? Your answer should be a base-10 integer. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 3.4: Well-formed State Diagram [2.5 points] Consider a node in the state diagram of a finite state machine. Let this node have n outgoing edges corresponding to the next state transitions from this state. Let C1 , C2, . . . Cn be the boolean expressions (in terms of input signals) corresponding to the trigger conditions for these edges. From the statements below, select the smallest subset of statements necessary and sufficient for the state transitions (including their triggers and actions) to be well-formed. By well-formed, we mean the resulting FSM does not exhibit an error. 1. ¿ |cj = 1, Vi, j € 1, 2, · n, i + j 2. ¿ &c; = 1, Vi, j € 1, 2, · n, i + j https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 8/20 pset3-2024-spring_58_1717053712071.ipynb - Colab 30/05/2024, 13:55 3. C1 &c2 & . . . &Cn = 1 4. ¿ &c; = 0, Vi, j € 1, 2, · n, i + j 5. C1|C2 | .|Cn = 0 6. C1 &c2 & . . . &Cn = 0 7. C1 C2 ··· Cn = 1 8. Ci |Cj = 0, Vi, j € 1, 2, . . . n, i + j Your answer should be a list of decimal integers corresponding to the choices necessary and sufficient for well-formedness. The list may be empty (write it as []), have only one element (e.g., [1]), or may have multiple elements (e.g., [1,2,3]). Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Problem 4: Optimizing States [10 points] Consider an FSM with one 1-bit input and one 1-bit output whose state table is shown below. In the table, PS, NS, x, and z represent the present state, the next state, the input, and the output respectively. https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 9/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab NS, z PS x = 0 x= 1 A E, 0 D, 1 F, 0 D, 0 B C E, 0 B, 1 D F, 0 B, 0 E C, 0 F, 1 F B, 0 C, 0 (Note: if an image doesn't show up above, please click on this link). v Part 4.1: All Equivalent States [4 points] Using the implication chart approach, identify all the equivalent states, list them below in the required format. For your convenience, we have placed a blank implication chart as a google doc at this URL. You can make a copy and fill it out or use scratch paper. You'll need to provide images of the Implication Chat after every step to show your work and provide us with a URL in the next part. Your answer should be in the form of a list of tuples where each tuple corresponds to a set of 2 or more equivalent states. Say you find that states A, B, and C are equivalent, and states D and E are also equivalent, then you'll write [(A,B,C),(D,E)]. If there are no equivalent states, your answer will be the empty list []. Enter_your_answer_in_required_format Optional Explanation: https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 10/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab Replace this text with your explanation. v Part 4.2: URL to Implication Chart Images [3 points] Put images of your implication charts (initial and after every step) into a single PDF file (you can use JPG or PNG if all your work is in a single sheet of paper), put that file on Google Drive, make it world-readable via sharing settings, and provide the URL below. You may use any other cloud service, such as Dropbox or OneDrive, as long as you can provide a world-readable URL. Put the URL in the answer cell below. Enter_your_answer_as_freeform_text (Markdown allowed) v Part 4.3: How many states after reduction? [3 points] How many states will the optimized FSM have, after merging equivalent states? Your answer should be a base-10 integer. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Problem 5: Latches and Flip Flops [10.0 points] v Part 5.1: When does SR Latch remember? [2 points] Consider the circuit below, which is an S-R latch gated with an enable signal E. https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 11/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab R + Q E S (Note: if an image doesn't show up above, please click on this link). Which combinations of E, S, and R does the circuit remember the current value of Q? 1. S=1, R=0, E=1 2. S=0, R=1, E=1 3. S=0, R=0, E=0 4. S=0, R=1, E=0 5. S=1, R=1, E=1 6. S=0, R=0, E=1 7. S=1, R=1, E=0 8. S=1, R=0, E=0 Your answer should be in the form of a list of option # from below, including all the correct ones and no incorrect ones. For example, your answer could be [] to indicate that no option works, [2] to indicate that only option 2 works, an [2,4,5] to indicate that only options 2, 4, and 5 work. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 5.2: Gated D Latch [2 points] Related to the gated S-R latch circuit is a gated D latch circuit shown below: https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 12/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab D Da Q E 10 De (Note: if an image doesn't show up above, please click on this link). At time t, E and D become E=0 and D=0. Furthermore, let Q be the current value of output signal Q just before that instant. What is the new logic value on Qb? Your answer would be either a boolean logic constant (0, or 1), or a logic expression (using the standard operators &, |, and ~, and parenthesis) in terms of Q and/or ~Q. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 5.3: JK Flip-Flop from T Flip-Flop [1.5 points] You are given one T Flip-Flop with input T and output QT, and need to make a JK Flip-Flop out of it with inputs J and K, and output Q. You are allowed to use any combinational logic in addition to the T Flip-Flop. Think of the JK Flip-Flop as a sequential system being built using one T Flip Flip and combinational logic. Derive the boolean logic expressions for T and Q in terms of J, K, and QT (not all three may be needed). In other words, write boolean logic expressions for combination logic functions that generate T and Q using J, K, and QT. You will write the expression for T in this part and for Q in the following part. Note that your design is considered correct only if the two expressions together work to form a JK Flip-Flop. Write the logic expression for T in the cell below. Use standard boolean operators &, |, and ~ in your answer, and parenthesis '(' and ')' as necessary. Your answer must be just the expression without any "T=" in the expression. https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 13/20 Qb 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 5.4: JK Flip-Flop from T Flip-Flop (contd.) [0.5 points] Continuing with the previous part, write in the cell below the logic expression for Q. Use standard boolean operators &, |, and ~ in your answer, and parenthesis '(' and ')' as necessary. Your answer must be just the expression without any "Q=" in the expression. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 5.5: JK Flip-Flop Behavior [2 points] Consider a JK Flip-Flop with initial state Q=1, and the inputs J and K at each clock tick as per the table below. Clock Cycle J Input K Input Q Output 0 - - 1 1 1 1 2 0 1 3 1 1 4 1 1 5 0 0 What are the values of Q right after clock ticks 1 through 5? Give your answer as a comma- separated list with five elements, where each element is 0 or 1 or X (to indicate unknown). E.g., your answer could be [0,1,0,x,1]. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 14/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab v Part 5.6: D Flip-Flop Behavior [2 points] Consider the following sequential circuit and assume that the D Flip-flops are ideal with zero delays, setup and hold times (i.e., ts = th = tcCQ = tacQ = 0). Also, please ignore the default values shown in the input and output pins when you answer the question. WE O 0 D2 MUX DSQ MUX DSQ F2 0 0 R R D1 MUX DSQ 0 MUX DSQ F1 0 0 R R O 0 MUX DSQ MUX DSQ 0 FO DO Ob 0 0 R R sysclk (Note: if an image doesn't show up above, please click on this link). Assume that WE = 1 throughout and that at rising clock edge #1, 2, and 3, D2D1D0 = 101, 010, and 000, respectively. What is the value of F2F1F0 after rising clock edge #3? Write your answer as a bit vector of 3 bits (the bits maybe 0, 1, or X for unknown) where the leftmost bit is F2 , the middle one is F1 , and the rightmost one is F0 . E.g., an answer of 1X0 will indicate F2 = 1 , F1 = unknown, and F0 = 0 . Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Problem 6: Finite State or Not? [10.0 points] https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 15/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab The concept of state in sequential systems is critical. In a finite number of bits stored in a state register at a given time, the state encapsulates all the relevant information about the previously observed inputs since the system started. The system uses the information in the state to determine future behavior based on new inputs. However, not all problems can be solved using a state expressed in a finite number of bits; some problems inherently require the entire observed history of inputs, which keeps growing ad infinitum as time passes. In each of the subparts below, we present a problem, and you need to think about and decide whether it can be solved in a system with a finite number of states. You would need to provide a sufficiently rigorous justification. Specifically, if you believe the problem can be handled by a sequential system with a finite number of state bits (and thus a finite number of states), describe informally what the states will be and how the system will work. Otherwise, if you believe that a finite state machine cannot handle the problem, then argue why not. We are looking for not more than a paragraph, hopefully a short one. v Part 6.1: Parity Checker [2.5 points] Consider a digital system that receives 0 or 1 on its one-bit input and determines the parity (odd or even) of the bit-vector formed by the bits received thus far. Can this be implemented using a finite state machine with a fixed number of state bits? Explain your reasoning. Answer in the next cell. Enter_your_answer_as_freeform_text (Markdown allowed) v Part 6.2: Detecting Palindromes [2.5 points] Consider a digital system that receives 7-bit ASCII characters on its input. At any time instant t it outputs a 1 if the string formed by all the characters received thus far is palindromic (a palindrome is a word, number, phrase, or a sequence of symbols that reads the same backward as it does forward, e.g., ECE, madam, Hannah, and the famous palindromic sentence by Napoleon 'Able was I ere I saw Elba.' Can this be implemented using a finite state machine with a fixed number of state bits? Explain your reasoning. Answer in the next cell. Enter_your_answer_as_freeform_text (Markdown allowed) https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 16/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab v Part 6.3: Detecting Prime Numbers [2.5 points] Consider a digital system that thinks of all the input bits received thus far at a time instant t as an unsigned number X, with the latest input bit being the least significant bit of X, and the oldest input bit being the most significant bit of X. At any instant t, the system's output F is 1 if the X is a prime number, and 0 otherwise. Can this be implemented using a finite state machine with a fixed number of state bits? Explain your reasoning. Answer in the next cell. Enter_your_answer_as_freeform_text (Markdown allowed) v Part 6.4: Detecting Unlucky Numbers [2.5 points] Consider a digital system that thinks of all the input bits received thus far at a time instant t as an unsigned number X, with the latest input bit being the least significant bit of X, and the oldest input bit being the most significant bit of X. At any instant t, the system's output F is 1 if the X is divisible by 13 and 0 otherwise. Can this be implemented using a finite state machine with a fixed number of state bits? Explain your reasoning. Answer in the next cell. Enter_your_answer_as_freeform_text (Markdown allowed) v Problem 7: Analyzing Timing [15 points] Consider the following sequential circuit when answering the various subquestions below: X DSQ DSQ DSQ DSQ F 0 O O O . R 9 R 0 R R . O sysclk (Note: if an image doesn't show up above, please click on this link). Each of the edge-triggered D flip-flops has a setup time of ts, a hold time of th, a propagation delay of tacQ = 4 ns, and a contamination delay of tccQ = 2 ns. Assume that X meets setup https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 17/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab and hold time requirements and that the clock frequency is 100MHz. v Part 7.1: Constraint on set up time [2 points] For the circuit shown above to operate correctly, what constraint on ts is necessary? For example, an answer might say ts > 8 ns or t2 ≤ 8 ns. Note: This question will be graded manually. Enter_your_answer_as_freeform_text (Markdown allowed) Optional Explanation: Replace this text with your explanation. v Part 7.2: Constraint on hold time [2 points] For the circuit shown above to operate correctly, what constraint on th is necessary? For example, an answer might say th > 8 ns or th ≤ 8 ns. Note: This question will be graded manually. Enter_your_answer_as_freeform_text (Markdown allowed) Optional Explanation: Replace this text with your explanation. v Part 7.3: Waveform Timing [2 points] Consider the following waveform plot for the circuit above. Assume that the input X is always stable from ts before the rising edge of the clock to th after the rising edge of the clock and that the time instant T is more than tacQ after the immediately preceding rising edge of the clock. What are the states of the D flip-flops from left to right at time instant T? https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 18/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab sysclk X Time=T (Note: if an image doesn't show up above, please click on this link). Your answer will be a bitvector of length=4, e.g., 0X10, where the leftmost bit indicates the state of the leftmost DFF in the circuit, and the rightmost bit indicates the state of the rightmost DFF in the circuit above. Use X to indicate that the state of a DFF is unknown. Note: The light gray vertical dotted lines are just a time grid and do not represent clocks. The clock signal is given explicitly as the waveform for sysclk. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 7.4: Reasoning about ts and th [3 points] Consider the circuit below where CL is some combinational logic block whose contamination and propagation delays are both 20 ps. The DFF has setup and hold times that are both 2 ps. X DIN . .. tc=td=20. . . . DOUT DSQ Z CL O R t$=2,th=2 sysclk 5 (Note: if an image doesn't show up above, please click on this link). Assume a clock edge occurs at t = 100 ps. In what time window would X need to be stable so that the stable value of X in that time window will be successfully stored in the DFF by the clock edge at t = 100 ps? Your answer should be a list of two decimal numbers without units, e.g., [98,102], where the first number indicates the start of the time window in which X must be stable (98 ps in our example) and the second number indicates the end of the time window in which X must be stable (102 ps in our example). For credit, both answers should be correct. https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 19/20 30/05/2024, 13:55 pset3-2024-spring_58_1717053712071.ipynb - Colab Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 7.5: Reasoning about ts and th (contd.) [3 points] One can think of the setup time ts and the hold time th as defining an interval [tedge - ts , tedge + th] (where tedge is the time instant that the clock edge occurs) during which a signal must be stable for the flip-flop to store the value successfully. Moreover, ts and th may be negative, and all that matters is that tedge - ts ≤ tedge + th. Based on your answers to the preceding sub-question, what are the set-up time and hold time for X? Your answer should be a list of two decimal numbers without units, e.g., [-2,5], where the first number indicates the setup time of X in ps (-2 ps in our example) and the second number indicates the hold time X (= 5 ps in our example). For credit, both values need to be correct. Enter_your_answer_in_required_format Optional Explanation: Replace this text with your explanation. v Part 7.6: Reasoning about ts and th (contd.) [3 points] A daniamanmondifind the Al an that an alassen in the finsing ita mantam in - and - https://colab.research.google.com/drive/1ou1VLU5PHAoq0uCKVW7TnSKGGBZOTvrN#scrollTo=Qtp5F0f2mUot&printMode=true 20/20See Answer
Q2:::: 4. For the parallel adder in the Figure, determine the complete sum by analysis of the logical operation of the circuit. Verify your result by longhand addition of the two input numbers. 34 A B C танск 7. The circuit shown in the Figure is a 4-bit circuit that can add or subtract numbers in a form used in computers (positive numbers in true form; negative numbers in complement form). a) Explain what happens when the Add /Subt. input is HIGH. b) What happens when Add /Subt. is LOW? Add/Subs O- ABC C ABC ABC 2 Σ ΣSee Answer
Q3:Problem 7: (8 pts) We have found a minimum sum of products expression for each of two functions, F and G, minimizing them individually: i. ii. iii. F=W'Z+W'Y+WX'Y' + WZ' G=W'X'Z+XY+XZ+WY'Z' + WX Implement them with a single PROM. Implement them separately with a single 8:1 Multiplexer for each. For the same functions, we have available as many of the decoders described below as we need plus 2 multi-input OR gates. Show a block diagram for this implementation. All inputs are available both uncomplemented and complemented. ENI EN2 AB 0123 0 XX0000 XX0000 1 001000 X 1 X 0 0 1 0 1 0 1 010100 A 1000 10 11000 1 B EN1 -a EN2 AB 1 8723See Answer
Q4:10. [5 pts] Draw the output waveform of a Gated D-latch (Q1) which is a level-1 triggering latch. G is a gate signal. Input D G Output Q1See Answer
Q5:7. [10 pts] Mealy sequential machine has following state table: NS Z PS| X=0 X = 1|X=0 X = 1 123 2 3 CLK X PS 2 221 N 2 1 321 1 3 2 Complete the following timing diagram. Clearly mark on the diagram the times at which you should read the values of Z. All state change occurs after the rising edge of the clock. You should put 1, 2 or 3 for PS and NS, and 0 or 1 for Z (for each half-cycle). Initial states given below. and values are 1 1 NS 2-3 0--0 0 0 1 0 0 0 1 I I T 1 I " T I 1 I 1 I I I I 1 1 1 ISee Answer
Q6:6. [10 pts] Below circuit is a S-R latch which uses NOR gates. Design a S-R latch using NAND gates and provide a truth table for the S-R latch. S R [S-R latch] P Q S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 [Truth Table] Q+ 0 1 0 0 1See Answer
Q7:ECE 2411 [ Spring 2024] Logic Circuits II 4. [10 pts] Derive the state transition table and D flip-flop input equations for a counter that counts from 1 to 5 and then repeats. HW #1See Answer
Q8:Homework #1 Full score: 100 pts 1. [15 pts] A Circuit examines a string of 0's and 1's applied to the X input and generates an output Z=1 only when the input sequence is 110. The input X and the output Z change only at rising edge of the clock. Derive (a) state diagram (Mealy sequential logic), (b) state table & transition table, (c) D flip-flop input and output Z equations for the sequence detector logic (provide the Karnaugh map). Also, (d) provide logic circuits for the Mealy sequential circuit. Below is a sample input sequence X and output Z: X= Z= 00011000011001100 00000100000100010See Answer
Q9:Problems: Part C-DeMorgan's and Don't Cares 10. For the following expressions, apply DeMorgan's Law to define an equivalent expression. a. (ab') = ?? b. (a + b')' = ?? c. a'b = ?? d. a' + b + c = ??; DeMorgan's can apply to more than two terms. e. (a'(b+c)')' = ??See Answer
Q10:9. Use a 4-variable K-map like the one shown here to determine the simplified expression for each given equation, x = f(a,b,c,d). Show ab the K-map circles used to perform reduction and define the final, simplified equation for x. If an expression cannot be simplified by the K-map, explain why. These equations are chosen to show the variety of circling challenges you can expect to encounter. a. x = a'b'c'd' + a'b'cd + a'bc'd' + a'bcd' + abc'd' + abcd' + ab'c'd' + ab'cd b. x = m1 + m3 + m4 + m5 + m6 +m7 + m9 + m11 + m12 +m14 ab c. x as defined by the K-map below; hint can be simplified into 2 circles cd 00 01 11 10 cd 00 01 11 10 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 00 01 11 10 00 01 11 10See Answer
Q11:8. Use a 3-variable K-map like the one shown here to determine the simplified expression for each given equation, x = f(a,b,c). Show the K-map circles used to perform reduction and define the final, simplified equation for x. If an expression cannot be simplified by the K-map, explain why. These equations are chosen to show the variety of circles you can expect to encounter. a. x = a'b'c + a'bc + ab'c' + abc b. x = a'b'c' + a'b'c + a'bc' + a'bc + abc' + abc c. x = a'b'c' + a'bc' + ab'c' + ab'c + abc' (0) a bc 0 1 00 01 11 10See Answer
Q12:tap here to 3. The K-map here plots r = f(p, q) with four cells labeled A, B, C, D. a. What minterm is represented by cell (C)? b. Which cell represents minterm p'q'? c. Which two cells differ in exactly one variable from cell (B)? Click or tap here to enter text. 0 1 0 AB 1 CDSee Answer
Q13:19. Using Boolean algebra techniques, simplify the following expressions as much as possible: a. A(A + B) b. A(A + ABSee Answer
Q14:40. Use a Karnaugh map to find the minimum SOP form for each expression: a. ABC + ABC + ABC b. AC (B+C) BC). c. A BC + BC + A (BC + BC)See Answer
Q15:5. Find the values of the variables that make each product term 1 and each sum term 0. b. ABCSee Answer
Q16: I. II. III. IV. ● Objective: Build and observe functioning of a S'-R' and S-R latches Build and observe functioning of a J-K flip-flop Parts List: S-R latch (Active-High Input): ● ● ● ● S'-R' latch (Active-LOW Input) ● ● ● ● J-K flip-flop: ● ● EET130 Digital Systems I Lab: Latches and Flip-flops 2 - 7402N Quad 2-input NOR gates 1 - 1 KOhm resistor 2- SPDT switches 2 - Digital probes 1- VCC (5V) 1 - GND ● 2- 7400N Quad 2-input NAND gates 1 - 1 KOhm resistor 2-SPDT switches 2 - Digital probes 1 - VCC (5V) 1 - GND School of Engineering Technology 2021 1 - J-K flip-flop 1 - 1 KOhm resistor 2-SPDT switches (to control preset and clear inputs) 1 - Clock voltage (to generate clock signal for flip-flop 2 - Digital probes 1 - VCC (5V) 1 - GND Procedures: Introduction: Both latches and flip-flops are considered as sequential circuits and can act as data storage devices. In these circuits current output depend on not only the current inputs but also on previous outputs. This experiment demonstrates the function of S-R and S'-R' latches as well as J-K flip- flops. 1. Construct the circuit shown in Figure 1(a) using components listed in parts list for S-R latch. 2. Change input S and R by changing SPDT switches and observe outputs Q and Q' using digital probes. 3. Write down results using Table 1. 4. Repeat steps 1-2 for S'-R' latch (Figure 1(b)). 1 5. Write down results using Table 2. 6. Construct the circuit shown in Figure 2 (top) using components listed in parts list for J-K flip- flop. 7. Change inputs preset and clear as shown in Figure 2 (bottom) and observe outputs Q and Q' using digital probes. 8. Write down results using Table 3. 0 0 1 S' 0 0 1 R R 0 0 (a) Active-HIGH input S-R latch (b) Active-LOW input S-R latch Figure 1: (a) S-R latch, (b) S'-R' latch 1 R' ē 1 School of Engineering Technology 2021 R Table 1: S-R latch results Q 2 Table 2: S'-R' latch results ē Q² Q' (a) (b) Clock 0 1 0 1 0 1 0 CLK PRE CLR Preset' 0 0 0 0 0 1 Preset HIGH J 3 K 1 1 1 1 1 Figure 2: J-K flip-flop Table 3: J-K flip-flop (' indicates bar) Clear' 1 School of Engineering Technology 2021 PRE 1 C CLR Q ē Toggle ♫ Clear Q² 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 1 1 0 0 0 School of Engineering Technology 2021See Answer
Q17: I 10. How many comparators are required 4 1 to form an 8-bit flash converter? པས:--སྡ°ང་ the bine. ז'יז 13. For a certain 2-bit successive-ap- proximation ADC, the maximum lad- der output is +8 V. If a constant +6 V is applied to the analog input, deter- mine the sequence of binary states. for the SAR. 14. Repeat Problem 13 for a 4-bit suc- cessive-approximation ADC. 17. Determine the output of the DAC in Figure 12-48(a) if the sequence of 4-bit numbers in part (b) is ap- plied to the inputs. The data inputs have a low value of 0 V and a high value of +5 V. 200 ΚΩ Dow 100 ΚΩ DOW 50 ΚΩ D₂ W 25 ΚΩ D3W (a) 10 ΚΩ ww Do D. D₂ Output D3 (b) Figure 12-48 18. Repeat Problem 17 for the inputs in Figure 12-49. Do D1 D2 D3 24. Fill in the appropriate functional names for the digital signal process- ing system block diagram in Figure 12-51 Figure 12-51See Answer
Q18:3. For the input shown below, show the flip flop outputs. a. Assume that the flip flop is a D flip flop without a clear or preset. b. Assume that the flip flop is a D flip flop with an active low clear. c. Assume that the flip flop is a D flip flop with active low clear and preset inputs. d. Assume that the flip flop is a 7 flip flop with the same input as part a, and that Q is initially 0. e. Assume that the flip flop is a 7 flip flop with an active low clear and the same inputs as part b. Clock Dor T b. and e. CLR' c. CLR' PRE'See Answer
Q19:6. We have a new type of flip flop, with inputs A and B. If A = 0, then Q* =B; if A = 1, Q* = B'. a. Show a state diagram for this flip flop. b. Write an equation for Q* in terms of A, B, and Q.See Answer
Q20:2. Use a 4:1 MUX and a minimum number of external gates to realize the following function. F (w, x, y, z) = m3 + m4 + m5 + m7+m10 + m14+ d1 + d6 + d15.See Answer

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