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Topics Concepts
Circuit Elements Resistors, capacitors, inductors, voltage sources, current sources
Electronic Components Transistors, diodes, operational amplifiers (Op-Amps)
Analog Simulation Continuous-time simulations, AC and DC analysis, transient analysis
Digital Simulation Logic gates, flip-flops, digital signal processing
Mixed-Signal Simulation Integration of analog and digital components in a single simulation
Power Electronics Switching circuits, power supplies, converters
Control Systems Feedback systems, PID controllers, stability analysis
Communication Systems Signal modulation, demodulation, RF circuits

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  • Q1:ECE 2020 Simulation Based Lab 2 DIGITAL FSM CIRCUIT MODELING AND SIMULATION WITH MULTISIM Multisim is a schematic capture and simulation program for analog, digital and mixed analog/digital circuits, and is one application program of the National Instruments "Circuit Design Suite", which also includes printed circuit board design tools and an interface to the ELVIS breadboarding platform. In this simulation-based lab, we will be using Multisim to perform simulations of digital circuits. Before getting started on the lab, we need to accomplish two tasks. 1. Install Multisim 2. Complete the Pre-lab assignments. Once you have installed Multisim and completed the Pre-Lab assignment, we will work on modeling and analyzing digital finite state machine (FSM) circuits using Multisim. The basic steps in modeling and analysis of a FSM circuits are: 1. Open Multisim and create a "design". 2. Draw a schematic diagram of the circuit (components and interconnections). 3. Define digital test patterns to be applied to the circuit inputs to simulate the circuit and connect signal sources to the inputs to produce these patterns. 4. Connect the circuit outputs to one or more indicators to display the response of the circuit to the test patterns. 5. Run the simulation and examine the results, copying and pasting Multisim windows into lab reports and other documents as needed. 6. Save the design. 1. Installing Multisim See separate document that was posted with Lab 1 on installing MULTISIM/LABVIEW. In ECE 2020, we will use MULTISIM only. 2. Tutorial on Multisim Please refer to the Multisim tutorial from Lab1. We are going to use the same techniques in this lab as well. 1 3. Pre-lab Assignment (Complete your work on a separate document and upload along with your lab work) Background: States: A = 00, B = 01, C = 10, D =11 where the states are defined by the values stored in the registers; for example, State B corresponds to S1S0 = 01 where S1 is the value of Register 1 and S0 is the value of Register 0. The next state for values of the registers is defined by NSI for Register i. For example, if the current state is B and the next state is C, then S1S0 = 01 and NS1 = 1 and NS0 = 0. External input: The external input in this circuit is denoted as "X". 3-to-8 Decoder with non-inverting inputs: Signals A0 - A2 represent the inputs and Y0 - Y7 represent the outputs. The convention is that A2 represents the most significant bit of a binary number and A0 represents the least significant bit; for example, an input of 011 is designated as A2A1A0 = 011. 2 Yo Ao Y1 A1 3 to 8 Y2 decoder Y4 Y3 A2 Y5 Y6 Y7 Fig. 1 (a): 3x8 Decoder with non-inverting outputs 3-to-8 Decoder with inverting inputs: The 74138 decoder (that you can find in your actual kit) has inverted outputs, so in the Pre-lab as well as the Multisim Lab, we are going to use a decoder with inverting outputs. YOO A0 Y1 A1 Y2 A2 Y3 b- Y40 Decoder Y5 16 Fig. 1 (b): 3x8 Decoder with inverting outputs 2 PRE-LAB PROBLEMS 1) Fill out the state transition table for the given state machine: X=0 A X=1 B (00) (01) X=0 + X=1 X=1 X=0 X=0 D C (11) X=1 (10) 3 STATE S1 So X NEW STATE |NS1 NSo A 0 0 0 A 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 3 2) Draw the circuit for your state machine below using Decoders and 2-input NAND gates as well as Flip-Flops. It is mandatory to use a Decoder whose outputs are inverted. Remember that decoders using inverted outputs and NANDs are functionally the same as decoders using non- inverted outputs and ORs. 4 4. MULTISIM portion of the Lab. Lab (1): Building a 3-state FSM. a) The state transition diagram for this state machine is shown in Figure 2. 5 5 X=1 A (00) X=1 X=0 X=1 C B (10) X=0 (01) X = 0 Fig. 2: State Transition Diagram for an example FSM. b) The state-transition table is shown below: A 0 0 0 B 0 1 A 0 0 1 A 0 0 State S1 So X New State 1 0 1 0 NS NS0 B 0 1 1 A 0 0 A 0 0 1 C 1 0 0 C 1 0 A 0 0 1 1 A 0 0 0 0 B 0 1 1 1 0 0 C 1 0 B 0 1 1 A 0 0 1 1 C 1 0 0 C 1 0 C 1 0 1 A 0 0 -- 1 1 0 -- -- -- -- 1 1 1 -- -- -- 5 c) The schematic below in Figure 3 shows the corresponding circuit. Input (X) So A0 YO D A1 Y1 To output probe A2 Y3 Y4 Y2 CLK D flip flop Decoder Y5 To output probe D C Y7 S1 D flip flop CLK Fig. 3: Circuit Diagram for Example State machine d) Implement the circuit in Fig. 3 using components in Multisim. You can use the techniques from Lab 1 to implement the combinational logic gates - inverter and NAND2. We are using the "Misc-Dig" Group and within the Group use the "TIL" Family. Apart from the inverter and NAND2, you will also need a 3x8 decoder (with inverted outputs) and 2 positive-edge triggered Flip-Flops. You can find these two components in the same Group (Misc Dig) and the same Family (TIL). You can use DCD_3to8 for the decoder and D_FF for the Flip-Flop. The D_FF will also come with two additional pins: a SET and a RESET. When SET=1, the output (Q) of the D_FF is set to "1". When RESET=0, the output (Q) is reset to "0". During normal operation both SET and RESET should be set to 0. Only when you are initializing the state-machine to a known state (say, 00), you will use the SET and RESET signals. Connect the input (X) to an input source. You can use the INTERACTIVE_DIGITAL_CONSTANT that we have used in Lab1. Connect the SET signals of both the Flip-Flops together and connect that to an INTERACTIVE_DIGITAL_CONSTANT. Similarly connect the RESET signals of both the Flip-flops together another INTERACTIVE_DIGITAL_CONSTANT. Thus, you can SET and RESET them together as needed. If you need to initialize the FSM to "01" or "10", then you will need to connect the SET and RESET signals of each Flip-flop separately to 2 different INTERACTIVE_DIGITAL_CONSTANT sources. Finally, connect the CLK of the two Flip-flops together and connect to another INTERACTIVE_DIGITAL_CONSTANT. Finally connect PROBEs to all the output nodes (S0 and S1 in this case). 6 Note: If you double click on any components, you will be presented with a menu. Under Label->RefDes you can change the name of the component. This will allow you to keep track of the signals. For example, the INTERACTIVE_DIGITAL_CONSTANT connected to the CLK input should be called CLK. Similarly for SET, RESET etc. Once, you are done, the Multisim schematic should look like this. SET 0. Key = Space So INPUT_X U6 2.5 V 1 U5 U7 SET Key = Space A YO. D . 0 B Y1. C Y2. Y3 NOT Y4. Y5 .RESET Y6. O Y7. b D FF 0 G. DCD_3TO8 S1 U1 C U8 2.5 V SET D NAND2 CLK . ~ Q 6- CLK RESET 0 D_FF Key = Space RESET 0 Key = Space Running the Experiment: Now you are all set to run the experiment. You can see that the simulation is setup in a manner that the CLK is not continuously generated. You will toggle the CLK input manually from 0 to 1 to 0 for every clock cycle. Since we are using positive- edge triggered Flip-flops, you will see changes at the output of the FSM (S0 and S1), when you toggle the CLK from 0 to 1 (i.e., the positive edge). To run the experiment, first RESET the outputs of both the Flip-flops to 0s. This indicates the State A from the State Transition Table. Next, keeping the CLK=0, set the correct input (X). You can set it to either 0 or 1. As a result the FSM to primed for the next state-transition. Next, toggle the CLK from 0 to 1 (at which point you will see the new state updated on S0 and S1), and then from 1 to 0. Now you are ready for the next state transition. Always remember to change the input (X) first keeping the CLK to 0. Then toggle the CLK from 0 to 1 and then finally to 0, to capture the state transition. Following this principle, fill up the Table 1 from the check-off Problem 1 in the next page. 7 Check-off Problem 1: As you run the simulations of the above circuit, observe the outputs (S0 and S1). Correspondingly identify the state of the FSM and fill up the Table below: Table 1: State A Input 0 State Input State Input State Input State Input State Input State Input 1 State 1 0 0 0 TA Initials: Lab (2): Implementing the Pre-lab state machine in Multisim. Now implement the pre-lab state machine in Multisim. Connect the sources and the PROBES to the circuit as required. Check-off Problem 2: As you run the simulations of the above circuit, observe the outputs (S0 and S1). Correspondingly identify the state of the FSM and fill up the Table below: Table 2: State A Input State Input State Input State Input State Input State Input State Input State 1 1 1 0 1 1 TA Initials: 8See Answer
  • Q2:(Draw #1) Using the following components (9V Battery, R1=22002, simple On/OFF switch S1, S2, S3 and a L.E.D.), First, draw a simple series circuit including a 9v battery (B1), switch (S1) and L.E.D. Make sure to connect the components with the correct polarities. Use "Snapping Tool" and capture the circuit screen (fig.1) for your lab report. Default position for S1 is ON (closed). (Draw #2) Draw the previous circuit then add S2 in parallel to B1. Use "Snapping Tool" and capture the circuit screen (fig.2) for your lab report. Default position for S2 is OFF (Opened). (Draw #3) Draw the previous circuit then add switch (S3) between (in series) the R1 and L.E.D. Use "Snapping Tool" and capture the circuit screen (fig.3) for your lab report. Default position for S3 is ON (closed).See Answer
  • Q3: OFFSET NULL- INVERTING INPUT- NON-INVERTING INPUT 11:49 LM741 Pinout Diagram W4 -Lab 4 Comparator-OL 2023-06.docx 8-NC OUTPUT OFFSET NULL Objectives: After completing this experiment, you should be able to, 1. Observe the behavior of Op-Amp as a comparator. 2. Build and test op-amp as a zero-level detector/sine-to-square wave convertor. Components needed: Instruments used: Submission Requirements: Submit the Multisim.ms 14 file along with your Experiment 4 lab document. 1. Potentiometers: 1k, 10k Multimeter (DMM) 2. Op-Amp: (1) LM741CN Oscilloscope Dashboard 4: Comparators 5G Procedure: 1. The LM741C is 8-pin op-amp. The pinout is shown in Figure 1. Observe there is a notch and a dot on the IC. The left side pin to the notch/dot is pin 1. 000 000 Calendar Figure 1: LM741 Pinout and Breadboard placing 1. Digital 2. Construct the following circuit shown in Figure 2 in MultiSim. Use voltage probes at both inputs and the output to measure the results for the first setting_in Table 1. 12 To Do 2. Notifications 6 Inbox 11:49 W4 -Lab 4 Comparator-OL 2023-06.docx Table 1: Calculated and measured values 6. Repeat step 3 through 5 for various voltage values at pin 3 and pin 2 as shown in rows 2,3, and 4 in Table 1. 7. Modify the above circuit as shown in Figure 3. Note that pin 3 is now connected to the function generator FGEN VCC 15V Dashboard 1kQ2 Pot -15.0V VEE VCC 15V -15.0V VEE waveforms 8. Set function generator to 10V, 1 kHz sinewave. PP' Figure 3: Op-Amp Comparator sine-to-square wave convertor Place Your Schematic Here U1 9. Connect CH_A of the oscilloscope to the input signal(pin 3) and CH B to the output (pin 6) of the comparator. 10. Tune the 1k2 potentiometer by observing the rectangular wave until you get a perfect square wave (with the amount of positive time being approximately the same as the amount of the negative time) as shown in Figure 4. (-50% duty cycle) 000 000 Calendar LM741CN 5G 5 Figure 4: Comparator input and output 11. Measure the DC voltage at pin 2 using a voltage probe. The measured voltage is 12 Place Your Scope Display Here To Do Notifications 3 Inbox 11:49 W4-Lab 4 Comparator-OL 2023-06.docx 2. Construct the following circuit shown in Figure 2 in MultiSim. Use voltage probes at both inputs and the output to measure the results for the first setting in Table 1. 10kΩ Pot Pin 3 Pin 2 Pin 6 V+ V- VOUT IV-IV VCC 15V 5V -6V -2V 7V -5V 10V -15:0V VEE Dashboard VCC 15V 1kQ Pot -15.0V VEE Figure 2: Op-Amp Comparator Place Your Schematic Here with voltage measurement probes Display results for row 1 of Table 1 I VCC 15V 3. Measure the voltage at pin 3 using a voltage probe and adjust the 10k potentiometer according to the voltage listed in Table 1. -15.0V VEE 4. Measure the voltage at pin 2 using a voltage probe and adjust the 1k2 potentiometer according to the voltage listed in the first row of Table 1. 5. Measure the output voltage at pin 6 using a voltage probe and record the result in Table 1. FGEN 000 000 Calendar U1 Table 1: Calculated and measured values LM741CN 6. Repeat step 3 through 5 for various voltage values at pin 3 and pin 2 as shown in rows 2,3, and 4 in Table 1. 5G 5 7. Modify the above circuit as shown in Figure 3. Note that pin 3 is now connected to the function generator VCC 15V 12 To Do Notifications 3 Inbox 11:49 W4 -Lab 4 Comparator-OL 2023-06.docx Oscilloscope-XSC1 Dashboard Place Your Scope Display Here 14. Now modify the circuit by reversing the inputs such that, the input signal connects to pin 2 and the potentiometer wiper connects to pin 3. Adjust the 1k pot to obtain a 50% duty cycle output. VCC 15V 1kQ Pot its -15.0V VEE FGEN ********* VCC 15V -15:0V VEE 000 000 Calendar Figure 5: Inverted Comparator Place Your Schematic Here 15. The observed phase shift between the input and output signal is degrees. Place Your Scope Display Here *** U1 LM741CN .5G 5 12 To Do *End of the experiment Notifications Inbox 11:49 W4 -Lab 4 Comparator-OL 2023-06.docx 11. Measure the DC voltage at pin 2 using a voltage probe. The measured voltage is 12. While measuring the DC voltage at pin 2, tune the 1kQ potentiometer so that the DC voltage value begins to go more negative. What effect does it have on the comparator output? Hint: Comment on the output duty cycle and the trigger level. Dashboard Sample scope display below. Write your observations below. Oscilloscope-XSC1 Place Your Scope Display Here Oscilloscope-XSC1 13. While measuring the DC voltage at pin 2, tune the 1k2 potentiometer so that the DC voltage value begins to go more positive. What effect does it have on the comparator output? Hint: Comment on the output duty cycle and the trigger level. Sample scope display below. Write your observations below. 000 000 Calendar 5G Place Your Scope Display Here X 12 To Do Notifications 5 3 InboxSee Answer
  • Q4: Objectives: After performing this experiment, you should be able to: 1. Construct and test the Wein-Bridge Oscillator for various values of R and C combinations. 2. Calculate and measure the frequency of oscillations. Submission Requirements: Submit the Multisim.ms14 files along with your Experiment 5 lab document. Components: 1. Op-Amp (1) 741C 2. Capacitors (2) 1µF, (2) 1nF, (2) 10nF, (2) 100nF 3. Resistors (2) 1.5k№, (3) 10k№, (1) 22kº Procedure: 1. Experiment 5: Wien-Bridge Oscillator For the circuit shown in Figure 1 below, calculate the frequency of oscillations using the formula below for the R, C values shown in table 1 below. Record the results in table 1 under calculated frequency. R 10 ΚΩ 1.5 ΚΩ C 1 nF 10 nF 1.5 ΚΩ 100 nF Vin(pp) @ pin 3 fr = Vout(pp) @ pin 6 1 2πRC Gain Av Calculated Freq. (fr) Table 1: Calculated and measured values Measured Freq. (fr) 2. Construct the circuit shown in Figure 1 in MultiSim. (Note: First build the op-amp amplifier circuit, then the output of the amplifier feeding input to the lead-lag circuit. Output of the lead-lag circuit is feeding to the input of the amplifier at pin 3.) Lead-Lag Circuit 2014 22:50 1179 2.... 251 252 SONY C4 1nF ..... R3 10kQ C1 HE 1nF Colchon 4₁: R2 www 10kQ R1 10kQ VCC (pin 51) 15V -15:0V 2 Figure 1: Wein-Bridge Oscillator Place Your Schematic Here U1. Go To VEE (pin 52) 1.00k-Pot LM741CN C2 DE 1μF MASA 26 ....... C3 DE 1μF 728 37 2000 2001 BER S 3. 4. 5. 6. 7. 8. Connect the output (pin 6) of the circuit to the Tektronix TDS2024 oscilloscope. Use the scope MEASURE settings to obtain the Vpp and Frequency measurements. Tune the 100k potentiometer so that you see a clear sine wave without any clipping. (Note: Depending upon where you are on the pot, you may need to turn the wiper a lot to see the signal. Change the potentiometer property settings so you can adjust by 1%) Measure the output voltage of the amplifier at pin 6 using the oscilloscope and record the results in Table 1 above under Vout(pp). Measure the frequency of the output sinewave and record the result in Table 1 above under measured frequency. Measure the input voltage of the amplifier at pin 3 using oscilloscope and record the results in Table 1 above under Vin(pp). Calculate the gain of the amplifier using the measured voltage and record the results in Table 1 above under the measured gain (Av). Av = Vout/Vin 3 FOUR CHANNEL Tektronix TDS 2024 DIGITAL STORAGE OSCILLOSCOPE Tek and has CH1 1V AA F Acq Complete M Pos: -20us CH2 5V M 20us CH1/ OV 12.7kHz Sample Scope Display R=10kQ, C=1nF 200 MHz 205/% MEASURE CH1 Pk-Pk 3.28V *********End of the experiment ********* 4 CH2 Pk-Pk 10.1V CH2 Freq 12.7kHz CH2 None Place Your Scope Displays (for each configuration here) Label them appropriately CH1 None 10. Replace the lead-lag circuit R and C values as listed in Table 1 above, and repeat steps through 9.See Answer
  • Q5:Experiment 4 - Part I: Boost Converter For the PV system shown below, the PV module produces a constant voltage of 12 V. The energy storage (ES) is made of lead-acid battery pack with a terminal voltage of 24 V. Design a DC-DC converter that converts the PV voltage to the ES bank voltage, i.e. from 12 V to 24 V. The maximum ripple in the converter's output voltage must be within ±0.5 V. ● ● DC/DC ES #70% ● DC/AC Grid Vin lin Vin L iL ip iin +s S ▷ Design a circuit that can meet these requirements. Show the simulation results for a few switching cycles for the current and voltage waveforms for all the components (switch, diode, inductor and capacitor). • At what duty cycle the converter must operate? If the PV voltage drops by 5%, 10%, 15% and 20%, explain how the converter would adjust its operation to meet the load requirement, i.e. 24 V output voltage. Support your answers with simulation results. D ic C iL Experiment 4 - Part II: Buck-Boost Converter In the previous system, another PV module is connected in series with the original one to increase the PV voltage. If the new PV voltage fluctuates by ± 50% throughout the day due to irradiance cloudy conditions variation throughout the day hours. Design a DC-DC converter that can operate under this wide input voltage window, i.e. 12 V-36 V. Show the simulation results for ± 10%, ±25% and ± 50% variation in the input voltage. The ripple in the output voltage must be within ±0.5 V. io K R iDSee Answer
  • Q6: Objectives: Lab 5: Time Proportioning Control After performing this experiment, you will be able to: 1. Control the average voltage/power delivered to the load using Time proportioning method. 2. Measure the duty cycle of the Pulse Width Modulated (PWM) signal. Procedure: 1. Construct the following circuit using multisim. R2 10ΚΩ Key=A 0% VCC 10V VCC 10V XSC1 A B U1 3 V1 + ཀ་ 5Vpk 60Hz 2 741 0° Offset = 5V Ext Trig Figure 1: Time proportioning circuit 2. Set the potentiometer to 0% and Run the simulation. Observe the oscilloscope; you should be able to see a positive DC voltage because the op-amp is saturated. Means the voltage at the non- inverting terminal is greater than the inverting terminal. 3. Measure the dc output voltage using the voltage probe at pin 6. Record the result in table 1 below under output voltage. 4. Set the potentiometer to 10%; you should be able to see the following waveform. Oscilloscope-XSC1 < T1+ T2 → T2-T1 Time 617.176 ms 630.054 ms 12.879 ms Channel_A Channel_B 9.118 V Reverse 9.118 V -297.448 uV Save Ext. trigger Timebase Scale: 10 ms/Div Channel A Scale: 5 V/Div Channel B Scale: 5 V/Div Trigger Edge: FABExt X pos. (Div): 0 Y pos. (Div): 0 Y pos. (Div): 0 Level: 1 V Y/T Add B/A A/B AC 0 DC AC 0 DC - Single Normal Auto None Figure 2: Measuring ON time of the pulse 5. Place the cursors 1 and 2 at the beginning and ending of the pulse as shown above. 6. Observe the value of T2-T1, which gives the ON time of the pulse. Record the result in the table 1 below under ON time (ton). Potentiometer setting Output ON Time (ton) Duty cycle Voltage 0% N/A 100% 10% 30% 60% 90% 100% N/A 0% Table 1: Duty cycle measurement 7. Now place the cursors such that time period (T) of the waveform can be measured as shown below. To measure the time period cursors must be place to cover one complete cycle. This time period will not change since the frequency of the signal stays at 60Hz. Oscilloscope-XSC1 Figure 2: Measuring time period of the waveform 8. The measured time period (T) is ¸ 9. Calculate the duty cycle using the formula below. Record the duty cycle in table 1 above. % DC = ton T * 100 10. Record the dc output voltage using the probe under output voltage. 11. Now, change the potentiometer setting as listed in table 1 above and repeat steps 5 through 10. Experiment Questions: 1. The term duty cycle refers to the amount of time a signal is compared to the period of one complete cycle. A. off B. on 2. The output voltage of op-amp is positive saturation, when the voltage applied to the input is greater than the A. inverting input. B. noninverting 3. A square wave that is 20V at its high state and OV when it is off will produce an average DC voltage of A. 7.5V when its duty cycle is 75%. Formula: VOUT = Duty Cycle * Peak voltage B. 10V C. 15VSee Answer
  • Q7: Objectives: Lab 4: Triode for Alternating Current (TRIAC) Operation 1. To verify the operation of TRIAC using DC triggering. 2. To demonstrate the phase control operation of TRIAC using AC triggering. Procedures: Part I: TRIAC Operation - DC Triggering 1. Construct the circuit as shown in the figure 1 using multisim. VCC 12V t -12.0V VEE VCC 12V S1 \Key = Space Basic >> Switch >> SPST S2 RA X1 12V_10W ⇒ Indicators >> Lamp >> 12V 10W ww 2.2ΚΩ Key = Space S3 D1 RB ww 10ΚΩ Key = Space 2N6073BG → Diodes >> TRIAC >> 2N6073BG S4 RC w 2.2ΚΩ Key = Space Figure 1: TRIAC Operation with positive voltage at MT2 2. Remember the TRIAC is a bi-directional device unlike SCR, which is unidirectional. a. It means we can have current flowing from MT2 to MT1 or MT1 to MT2. b. In the above circuit, we have current flowing from MT2 to MT1, since MT2 side held at VCC (using conventional current direction). 3. TRIAC can be ON with both positive and negative voltages at the gate. If you close switch, a. S2, positive voltage is applied to the gate. b. S3, OV is applied to the gate and c. S4, negative voltage is applied to the gate 4. Place the voltage probes at Gate and MT2 of the TRIAC to measure the DC voltage. 5. Change the position of the switches in order as listed under table 1 and record voltage at the gate, MT2 and TRIAC/Lamp condition either ON or OFF. Do not stop the simulation until you complete the table. Switch S1 Position Gate Switch Position Gate Voltage (VG) Voltage across TRIAC TRIAC/Lamp Gate condition Switch (VMT2-MT1) (On/Off) Position Close S1 Close S3 Open S3 Close S1 Close S2 Close S1 Open S2 Open S1 Close S1 Close S4 Close S1 Open S4 Open S1 Close S2 Table 1: Voltage values and condition of TRIAC 6. Modify the above circuit as shown in figure 2 below. Observe the switch S1 is connected to VEE. As mentioned in step 2, in this case the current will flow from MT1 to MT2. VCC 12V -12.0V VEE -12.0V S1 \Key = Space ⇒ Basic >> Switch >> SPST S2 RA w 2.2ΚΩ X1 12V 10W ➤ Indicators >> Lamp >> 12V 10W Key = Space S3 D1 RB w 10ΚΩ Key = Space 2N6073BG Diodes >> TRIAC >> 2N6073BG S4 RC w 2.2ΚΩ Key = Space VEE Figure 2: TRIAC Operation with negative voltage at MT2 7. Place the voltage probes at Gate and MT2 of the TRIAC to measure the DC voltage. 8. Change the position of the switches in order as listed under table 2 and record voltage at the gate, MT2 and TRIAC/Lamp condition either ON or OFF. Do not stop the simulation until you complete the table. Switch S1 Position Gate Switch Position Gate Voltage (VG) Voltage across TRIAC (VMT2-MT1) TRIAC/Lamp condition Gate Switch (On/Off) Position Close S1 Close S3 Open S3 Close S1 Close S2 Close S1 Open S2 Open S1 Close S1 Close S4 Close S1 Open S4 Open S1 Close S2 Table 2: Voltage values and condition of TRIAC Part II: TRIAC Phase control - AC Triggering 9. Modify the previous circuit as shown below. + กับ V1 10Vrms 60Hz 0° X1 ㄡˋ 12V 10W R1 3.3ΚΩ Key=A 0% R2 3.3ΚΩ C1 = 0.1μF MT1 MT2 D1 2N6073BG Figure 3: TRIAC Phase control - AC Triggering XSC1 B Ext Trig 10. Connect the channel A of the oscilloscope across the lamp and channel B across the TRIAC as shown above. 11. Change the color of the channel B wire by right clicking on the wire >> segment color >> blue. This way we can easily identify red color waveform is across the lamp and blue one is across the TRIAC. 12. Turn the potentiometer to 0%. 13. Run the simulation. Insert the voltage waveform across the lamp and across TRIAC below (use snipping tool. You need to separate both the waveforms using Y-pos. (Div) on the scope). 14. When the potentiometer at 0%, total voltage dropped across the TRIAC is the entire source voltage (where you will see full sinewave) and OV across the lamp (so lamp will be OFF). 15. Turn the potentiometer to 10%, while observing the voltage waveforms. 16. Insert the voltage waveform across the lamp and across TRIAC below. 17. Observe the waveform across the lamp (red waveform), it has the negative side as well, which implies the TRIAC is bidirectional. Therefore, the power will be delivered during positive and negative cycles as well unlike in SCR, where the power will be delivered during positive cycle only. 18. By increasing the potentiometer setting, TRIAC will be firing angle will be decreased and more power will be delivered to the lamp, means it will be more brighter. 19. Change the potentiometer in steps of 25%, take the screenshot of the oscilloscope image (use snipping tool), and insert below. Potentiometer @ 25%: Potentiometer @ 50%: Potentiometer @ 75%: Potentiometer @ 100%: Experiment Questions: 1. Before firing, the voltage across the TRIAC is a. OV b. Approximately Equal to power supply. 2. Once the TRIAC is turned on, it can only be turned off by. a. Removing gate voltage. b. Reducing the current flowing through TRAIC below the holding current value. C. Both a and b. 3. The TRIAC can be triggered on by applying. voltage. a. A positive at the gate b. A negative at the gate c. both a & b 4. How TRIAC is different from SCR? State your observations below.See Answer
  • Q8: Objectives: Unit 1 Lab Assignment 2 Silicon Controlled Rectifier (SCR) Operation 1. To verify the operation of SCR using DC triggering. 2. To demonstrate the phase control operation of SCR using AC triggering. Procedures: 1. Research the datasheet of 2N1599 SCR and fill the following table 1 at 25°C. Parameter IT(RMS) Forward current RMS IH - Holding current VDRM-Peak forward blocking voltage IGT -Gate trigger current (typical) IDRM - Peak forward blocking current VTM - Forward on voltage (typical) Table 1: Specifications of EC103D1 SCR Part I: SCR Operation – DC Triggering Value 2. Construct the circuit as shown in the Figure 1. (use jumpers as a switch) VCC 12V R1 680Q R2 10ΚΩ Lamps can be found under Indicators >> Lamp 12V 10W Anode D1 S1 Gate 2N1599 SCRS cane be found under Diodes >> SCR Key = Space Cathode Switches can be found under Basic >> Switch >> SPDT Figure 1: SCR DC Triggering 3. Connect the gate switch (S1) to R2, and then run the simulation. Do not stop the simulation until you complete table 2. 4. Measure the voltage at the gate terminal and record the measured value in the first row of the table 2 under gate voltage. 5. Measure the voltage between anode and cathode of the SCR and record the measured value in the first row of the table 2 under SCR voltage. 6. Indicate the condition of the SCR whether it is on or off based on the lamp condition. 7. Change the position of the switch in the order as indicated in table 2 below and repeat steps 4 through 6. Gate connection Gate Voltage (VG) SCR Voltage (VAK) SCR/Lamp condition (On/Off) R2 R1 R2 Table 2: Voltage measurements and condition of SCR Part II: Phase control of SCR - AC Triggering 1. Modify the previous circuit as shown below. Modify the number of turns to 12:0.5:0.5 by double clicking on the transformer ✗SC1 V1 120Vrms 60Hz 0° R1 1.4ΚΩ 12V 10W T1 000000• 7ΚΩ Key=A R2 12:0.5:0.5 0% Transformers can be found under Basic >> Transformers >> 1P1S_Tapped C1 1μF (y) D1 2N1599 Ext Trig ΟΙ Figure 2: SCR Phase control - AC Triggering 2. Turn the potentiometer (R2) to 0%, which represents the firing angle to be approximately 180º. Then Run the simulation. a. Since the firing angle is 180º, no power delivered to the lamp and it should be off. 3. The signals on the oscilloscope should be as shown below. Blue one across SCR & Red one across lamp (separate both signals so you can see them clearly). Oscilloscope-XSC1 < Time Channel_A Channel_B T1 0.000 s 0.000 V -0.000 V T2-> T2-T1 0.000 s 0.000 s 0.000 V 0.000 V -0.000 V 0.000 V Timebase Channel A Channel B Scale: 10 ms/Div Scale: 20 V/Div Scale: 20 V/Div X pos. (Div): 0 Y pos. (Div): 1 Y pos. (Div): -1.8 Y/T Add B/A A/B AC 0 DC O Reverse Save Ext. triggerO Trigger Edge: FZA Ext Level: 0 V AC 0 DC│||-|| O Single Normal Auto None Tauveu Figure 3: Oscilloscope waveforms 4. Change the potentiometer in steps of 25%, take the screenshot of the oscilloscope image (use snipping tool), and insert below. Potentiometer @ 25%: Potentiometer @ 50%: Potentiometer @ 75%: Potentiometer @ 100%: Answer the following Experiment Questions: 1. Before firing, the voltage from anode to the cathode is a. ον 2. If the gate is made on. b. Approximately Equal to Vcc. when the anode and cathode are forward-biased, the SCR turns a. Negative 3. The SCR will b. Positive when the gate potential is removed and the anode/cathode are forward- biased. a. Remain on b. Turn off 4. When the SCR is off, the voltage from the anode to ground is a. Close to VCC b. Near O 5. The SCR will turn off when the current flowing through it drops below the value./n Abstract: Introduction: Procedure: Analysis & Results: A brief description of the experiment. The abstract should not exceed four or five sentences. In your own words, motivate the experiment and give a concise summary of the theory involved, including any mathematical detail relevant to later discussion in the report. List and describe the steps for the practical lab. A schematic of the experimental setup is also required. This section should include all raw data collected, e.g., voltage and current readings. All results are to be presented in both tabular and graphical form. All tables must have titles and all figures must have brief captions. Clearly show your analysis steps and any calculations used leading to your Analysis & Results: Conclusion: required. This section should include all raw data collected, e.g., voltage and current readings. All results are to be presented in both tabular and graphical form. All tables must have titles and all figures must have brief captions. Clearly show your analysis steps and any calculations used leading to your results and conclusions. This section should reflect your understanding of the experiment conducted. Important points to include are a brief discussion of your final results, an interpretation of the actual experimental results as they apply to the objectives of the experiment set out in the introduction should be given. Also discuss any problems encountered and how they were resolved.See Answer
  • Q9: Lab Assignment 1 Part 1 Latches Objectives Use NOR and NAND logic gates to construct and operate S-R latches and D latches. Explain the operation of a basic S-R latch and Gated S-R latch. Explain the operation of a gated D latch ■ Explain the difference between an S-R latch and a D latch. Components ■ Multisim Circuit Simulator ■ 7400N 2 input NAND · 7402N 2 input NOR 7406N Inverter ■ Probe Introduction The latch is a type of temporary storage device that has two stable states (bistable) and is normally placed in a category separate from that of flip-flops. Latches are similar to flip-flops because they are bistable devices that can reside in either of two states using a feedback arrangement, in which the outputs are connected back to the opposite inputs. The main difference between latches and flip-flops is in the method used for changing their state. This experiment will demonstrate how a group of logic gates such as NOR and NAND compose latch circuit and act as a temporary information storage device. Procedure Step 1 Build the SR NOR Latch circuit in Figure 1 using Multisim and verify the operation of the circuit by changing the set and reset inputs. Pay attention to the state of Q and Q outputs while you change input combinations. Fill out the state table of the SR NOR Latch. VCC 5V 25V Reset U1A 7402N Key = Space U2A Set 7402N Key = Space Figure 1 SR NOR Latch S R Q ē 0 0 Qbar 0 1 2.5V 1 0 1 1 Step 2 Build the SR NAND Latch circuit in Figure 2 using Multisim and verify the operation of the circuit by changing the S and Ŕ inputs. Pay attention to the state of Q and Q outputs while you change input combinations. Fill out the state table of the SR NAND Latch. VCC 5V 2.5 V Setbar U1A S R Q Q 7400N Key - Space 0 0 Qbar T 0 1 2.5V 1 0 U2A Resetbar 7400N Key = Space 1 1 Figure 2 SR NAND Latch Step 3 Build the Gated SR NAND Latch circuit in Figure3 using Multisim and verify the operation of the circuit by changing the set, reset, and EN inputs. Pay attention to the state of Q and Ō outputs while you change input combinations. Fill out the state table of the Gated SR NAND Latch. VCC 5V Set 2.5 V U3A U1A S R EN 7400N Key - Space 7400N 0 0 1 EN Qbar 0 1 1 2.5 V Key - Space U2A U4A Reset 7400N 7400N Key = Space 1 0 1 1 1 1 X X 0 Figure 3 Gated SR NAND Latch 0 Step 4 Build the Gated D Latch circuit in Figure 4 using Multisim and verify the operation of the circuit by changing the D and EN inputs. Pay attention to the state of Q and Ō outputs while you change input combinations. Fill out the state table of the Gated D Latch. VCC 5V 2.5 V D U3A U1A D EN Q 7400N Key Space 7400N 0 0 EN Qbar 1 1 2.5 V X 0 Key= Space U2A U4A U5A 7400N 7400N 7406N Figure 4 Gated D Latch Submission: • • • • Save your Multisim simulation file as EET230_Lab#_YourName. Be sure Submit word document file (no zip file) All screenshots of Multisim must capture the date of the simulation. Attach each circuit file of your experiment's simulation separately.See Answer
  • Q10: Lab Assignment 5 Digital to Analog Conversion (DAC)/Analog to Digital Conversion (ADC) Objectives Study and implement of Signal Conversions Explain how DACs operate ◉ Explain how ADCs operate ■ Multisim Simulation Analysis of signal conversions Explain the basic concepts of a digital signal processor (DSP) Procedure Construct and use multisim to simulate analysis for the following ADC/DAC circuits. For each circuit, provide a couple screenshots, all screenshots must capture the date of the simulation. Digital to Analog Convertors Multisim Simulation 1) Binary Weighted Digital to Analog Converter Figure 1 shown below is a binary-weighted Digital-to-Analog converter. Build the circuit in multisim and answer the following questions in your simulation a) Close each switch individually to determine how many volts each switch contributes to Vout. List those four values in a data table. b) The current through If is always equal to Isum (T or F)? c) Which switches need to be closed to yield the following outputs: -8V, -4V, -6V, -11V? d) How many different digital numbers can be represented with the four input switches? e) To make a 5-bit D-to-A you would need to add another switch and resistor to the left of D3. What size would the resistor be? Digital Input Key= D3 Key = D2 Key-95 R1 Key -S1 .020u D1 DO V1 20kQ R 5V 12.5kQ 25kQ 50kQ R2100kQ FO R6 0.020u Figure 1 R3 Analog Vout OPAMP_ST_VIRTUAL 10kQ -0.400m ARI 2) Virtual DAC The DAC shown in figure 2 outputs a voltage proportional to its 8-bit binary input. The +Vref input is set to 5V. This in turn sets the maximum output at 5V. Since there are 256 possible binary input steps then the volts per step will be 5V / 256 = 19.53mV. The word generator is used to count from 0 to F repeatedly (the 4 high-order inputs are not used in this case) by doing the following steps: ➤ Single-click on the Word Generator icon in the far-right column of icons in the Multisim screen to put it in your workspace (XWG) and move it to where you want it ➤ Double-click on the Word Generator icon in your workspace ➤ In the pop-up window, click on Set ➤ In Preset Patterns, click on the Up counter button ➤ Type 0010 in the Buffer Size box ➤ Close the pop-up window ➤ To get XSC1 in your workspace, single-click on the Oscilloscope icon in the far-right column of icons ➤ To place the VDAC icon in your workspace, click on Place in the top menu bar, select Component, then type VDAC into the Component entry box a) Play with the oscilloscope's Timebase Scale and Channel A Scale until you get a reasonably- sized image of the full output. Take a screenshot. b) Change the Buffer Size in the Word Generator to 0100 so that all 256 steps will be output. Adjust the oscilloscope's Scales and take a screenshot. XWG1 ooo ooo ooo oo000000 O oooooooo oo000000 31 T VCC 5V Vref DO D1 D2 D3 D4 D5 D6 D7 U1 + VDAC VDAC XSC1 Analog Output Figure 2 3) R2R Ladder Digital to analog converter The circuit shown in figure 3 below is an R2R ladder. Observe the output for different input combinations. Carry out the calculation and check your calculated and simulated results Binary Input 1s R1 W 20ΚΩ Key = A V1 2s R2 3.2 V 0 20kQ Key = B R5 W 20ΚΩ R7 10kQ R8 10ΚΩ 4s R3 W 20ΚΩ R9 10ΚΩ Key = C 8s R4 ° ww 20ΚΩ Key = D R-2R resistor network Figure 3 1 2 R6 www 10ΚΩ U1 OPAMP_3T_VIRTUAL Analog Output Scaling Amplifier 0.200 4) Analog to Digital Converter Figure 4 below is used to convert the Analog Vin into a binary number at the output of the ADC. This binary output is displayed in hex on the two seven-segment displays. The Analog Vin is varied by changing the potentiometer setting (a and Shift-a). a) Create a data table of Analog Vin versus hex output for eleven steps in Vin from 0V to 5V in 0.5V increments. b) Convert all of your HEX answers to decimal. Do they appear to be taking approximately equal steps? 5V 1000 Key-A 50% Analog Vin U3 DCD_HEX U4DCD_HEX Hex Output U1 0.000 5V VCC VIN VREFP VREFN Soc Start pulses OE 8888888 DO D1 D2 D3 Digital Output D4 D5 D7 EOC + വ 10KHZ 5V A DC Submission: • • • • Figure 4 Save your Multisim simulation file as EET230_Lab#_YourName. Be sure Submit word document file (no zip file) All screenshots of Multisim must capture the date of the simulation. Attach each circuit file of your experiment's simulation separately.See Answer
  • Q11: Lab 3 - Uni-Junction Transistor (UJT) Operation Objectives: 1. To verify and plot the switching characteristics of UJT. 2. To demonstrate the operation of UJT as a relaxation oscillator. 3. To Measure the frequency of oscillations. Procedures: Part I: UJT Characteristics: 1. Construct the circuit as shown in the figure 1 using multisim. V1 -9V R5 500Ω Key=A 0% |: -- PR4 I (p-p): -- R1 15ΚΩ R3 470Ω Q1 I(rms): -- I(dc): -- I(freq): -- Current Probe Voltage Probe PR1 V: -- V(p-p): -- 2N6027 R2 51ΚΩ R4 470Ω V(rms): -- V(dc): -- V(freq): -- Transsitors >> UJT >> 2N6027 Figure 1: UJT test circuit 2. Adjust the R5 potentiometer to 0%. 3. Place current and voltage probes at the anode of the UJT as shown above. 4. Run the simulation and fill the following table by varying the potentiometer as listed under column 1. Potentiometer VA ΤΑ setting 0% 10% 20% 30% 40% 50% 60% 70% 80% 85% 95% 100% Table 1: Measured voltage and current values at the anode 5. Compare the values of VA and lÅ before and after firing (firing implying when UJT is ON). a. Prior to firing, as the VA increases ↳ increases until a voltage called as the peak voltage. From table 1, the peak voltage is b. After firing, là continues to increase whereas VA drops to a lower value called as the valley voltage. From table 1, the valley voltage is C. Since voltage decreases when current increases, this region of operation of UJT is referred as negative resistance region. 6. Based on the readings from the table 1, plot the graph between Anode current (IA) on X-axis and Anode voltage (VA) on the Y-axis. Note: Use word or Excel to plot the graph. Properly indicate the titles for each axis. Part II: UJT as Relaxation Oscillator 1. Modify the previous circuit as shown below. 5 500 V1 .9V R1 16ΚΩ Anode 33 R3 47ΚΩ PR1 Gate Q1 2N6027 V: -- V(p-p): -- V(rms): -- Cathode V(dc): V(freq): -- C1 R2 27ΚΩ R4 = 0.1μF 200 XSC1 B Ext Trig Figure 2: UJT Relaxation Oscillator 2. Record the frequency of oscillations in the table below by modifying the values of R3 and C₁ as listed below. Use the voltage probe to measure the frequency. Measured R3 C1 Frequency 47 ΚΩ 0.1 µF 68ΚΩ 0.1 μF 75ΚΩ 0.1 µF 75ΚΩ 0.01 μF 91 ΚΩ 0.01 µF Table 2: Measured frequency values 3. Connect the oscilloscope at Anode, cathode and gate and insert the waveform snippets (at least 3 cycles) for each of the terminal below using the values in the first row of table 2. Experiment Questions: 1. After UJT fires, VA 2. a. Increases A positive pulse train is found at a. Anode and IA b. Cathode b. decreases of a UJT oscillator c. Gate 3. The voltage waveform at is a sawtooth. a. Anode b. Cathode c. Gate 4. If the value of RE increases, the oscillator frequency a. Increases b. decreasesSee Answer
  • Q12:Experiment 6-Part II: Controlled Rectifiers A single phase full wave controlled rectifier is supplied from 1414-V (rms) 60-Hz supply and the load is highly inductive, which keeps the load current smooth and ripple free. The average load current l is 450 A. • Find the required firing angle for this current. . ⚫ Show the load voltage and current waveforms. • Explain what happens if the firing angle is increased or decreased. Support your answer with simulation results. 1414 V 60 Hz R-2.402 vo(t) io(1) L-0.6 HSee Answer
  • Q13: Miami Dade College Spring 2024---EET 1141C Mid-Term Exam To Be Concluded Without the Aid of any Assistance. NAME: MDC ID: Instructions: Read the Instructions carefully. Please Make Sure to conclude all Three Portions of the Design Examination without the Aid of anyone. Use the Provided Space to Show how you arrived at your results. The Use of a Calculator is permitted. Please Be Sure to show all the Process involved in arriving at your Design conclusions. You will be given a design Specification that is Unique to you alone. Do Not Compare Notes with Others. V2 15 V ~ C2 HH V1 1μF 0.005 Vrms 3kHz 0° R3 R2 www R4 U1 C1 H 10μF 2N3904 R1 C3 HH R5 100μF >R8 3-stage Cascaded Amplifier www R9 U2 C4 HH 10μF 2N3904 R6 R7 C6 R10100μF R13 U4 2N3904 C5 >R14 HH 100μF >R11 Using a series of steps, you will design a 3 stage Cascaded Amplifier Shown above that is Unique to you Alone and different from everyone else in the class. Question 1: Design of the Common-Emitter Amplifier Common-Emmitter Amplifier V1 -15 V V2 1mVrms 3kHz 0° C1 HH 10μF R2 RC U1 2N3904 >RE1 R1 Step 1: Acquiring Your Individual Specification: DC Bias values of Ic,Q and VCE,Q C2 HH 10μF RE C3 100μF 1 Rload Miami Dade College Spring 2024---EET 1141C Mid-Term Exam To Be Concluded Without the Aid of any Assistance. (last 2 digits of your MDC ID) Ic(mA) = 2 + 200 DC Bias Value of VCE (Last 2 digits of your MDC ID) VCE (V) = 6- 100 Choose the Swamping Resistor RE1 = 22 2 or 33 2; Emitter Bias Resistor RE = 1KQ and assume a Beta, ẞ= 150 for the Q2N3904 Record Your Specifications in the Spaces Provided Below VCE = IC= IB= IE= Step 2: Calculate the DC operating point of all the Transistor Terminals Using the Values above, Calculate the following (a) Emitter Voltage VE VE = (b) Base Voltage VB = (c) Collector Voltage; VC VC = (d) Collector Resistance, RC RC= 2 Miami Dade College Spring 2024---EET 1141C Step 3: Design the Voltage Divider Bias Circuit Mid-Term Exam To Be Concluded Without the Aid of any Assistance. Using the Principles of a non-stiff voltage divider Bias, that is using the Thevenin's equivalent Circuit, design R1 and R2 such that the design Values of VB and B are met. Show your calculations in the space provided below. R1= R2= Next calculate the AC-Model Emitter Resistance re of the BJT Using your design Quiescent operating. Assume that the operating temperature is 25°C re= Step 4: Calculate the Voltage Gain Next Using the value of re and your circuit parameters Calculate the Value of the ac or small-signal Voltage Gain Av. Av= Step 5: Simulation and Verification (a) Setup the Common-Emitter Amplifier on Multisim using your design parameters. Simulate the Circuit and display the DC operating point of the amplifier using the Multisim Probe feature. (b) Using an Input signal of 5mVrms Sinusoidal Signal at 3KHz, perform a transient simulation. Display the result for at least 5 Periods. (c) Perform an AC frequency sweep of the Amplifier from and Initial frequency of 1Hz to a final frequency of 100MHz. Your display window should be set to Decades and your initial gain in Decibels should be set to -50db and Final Gain to 50 decibels. Display the results. What is the maximum gain of your amplifier in Decibels? What is the maximum unitary gain? 3 Miami Dade College Spring 2024---EET 1141C Mid-Term Exam To Be Concluded Without the Aid of any Assistance. Question 2: Design of the Common-Collector Amplifier or Emitter Follower. Common Collector Amplifier V1 -15V ~ V2 1mVrms 3kHz 0° C1 = HH RB_Bias 10μF U1 2N3904 C3 HH RE3 100μF RLoad_final Using the Value of R1, R2 and RE from the Common-Emitter amplifier Circuit as Rcc_Bias1, as Rcc_Bias2 and RE3 and a large Resistor Value such as 100KQ for RLoad_Final. Step 1: Calculating the DC Bias and Quiescent Point Calculate the DC emitter Current. IE= Calculate the DC Collector Current IC= Calculate the DC Base Current IB= Next calculate the AC-Model Emitter Resistance re of the BJT Using your design Quiescent operating. Again, Assume that the operating temperature is 25°C. Miami Dade College Spring 2024---EET 1141C Mid-Term Exam To Be Concluded Without the Aid of any Assistance. re= Step 2: Calculate the Voltage, Current and Power Gain Next Using the value of re and your circuit parameters Calculate the Value of the ac or small-signal Voltage Gain Av. Av= Next; Calculate the Current gain A¡ of the Emitter Follower Ai= Finally Calculate the Power Gain of your Emitter Follower Ap=_ Step 3: Simulation and Verification (d) Setup the Common-Collector Amplifier on Multisim using your design parameters. Simulate the Circuit and display the DC operating point of the amplifier using the Multisim Probe feature. (e) Using an Input signal of 5mVrms Sinusoidal Signal at 3KHz, perform a transient simulation. Display the result for at least 5 Periods. (f) Perform an AC frequency sweep of the Amplifier from and Initial frequency of 1Hz to a final frequency of 100MHz. Your display window should be set to Decade increment of Frequency and your initial gain in Decibels should be set to -50db and Final Gain to 20 decibels. Display the results. What is the maximum gain of your amplifier in Decibels? What is the maximum unitary gain? Q3: The 3-Stage Cascaded Amplifier 5See Answer
  • Q14: Miami Dade College Spring 2024---EET 1141C Step 1: Acquiring Your Individual Specification: Ripple Voltage of the Filter Circuit: Name MDC ID Instructions: Read the Instructions carefully. Please Make Sure to conclude all Three Portions of the Design Examination. Use the Provided Space to Show how you arrived at your results. The Use of a Calculator is permitted. Please Be Sure to show all the Process involved in arriving at your Design conclusions. You will be given a design Specification that is Unique to you alone. Using a series of step you will design a DC Power supply that is Unique to you Alone and different from everyone else in the class. Question 1: Design of DC Power Supply with a Steady Output Voltage of 5.0Volts. ripple factor (%) = 10 DC Voltage of the Filtered Rectifier Vdc = 7 Line Regulation of the Zener Regulator in mV/V = 20 Ripple factor, ripple=_ Ripple Voltage V₁=_ Maximum Value of the Filtered Voltage, Vimax =_ Minimum Value of the Filtered Voltage, Vfmin=- Peak Value of the Rectified Signal, Vpeak = Peak Secondary Voltage of the Transformer, Vs=_ Turn Ratio of the Transformer, n =_ Exam 1 Record Your Specifications in the Spaces Provided Below Filter DC Voltage, Vdc = DC voltage of the Regulated Power Supply = Line Regulation for the Zener Voltage Regulator: = (last 2 digits of your MDC ID) × 4 100 (Last 2 digits of your MDC ID) 100 (Last 2 digits of your MDC ID)×10 100 To Be Concluded in 3 Hours Miami Dade College Spring 2024---EET 1141C Step 2: Design the Full-wave Bridge Rectifier and Filter Circuit shown in Figure 1 below Such that Your DC voltage and ripple factor meets the specification above. + V1 170Vpk 60Hz R₁: 0° Figure 1 T1 www D3 1N4001G D7 1N4001G Exam 1 D4 1N4001G D5 1N4001G ww Figure 2 R1 C1 To Be Concluded in 3 Hours Note that the Frequency of the Secondary transformer is 60Hz. Choose a Value of C1 that is readily available in the Laboratory and then design for the value of R1 such that your specifications above are met. Show your calculations below. C₁: Step 3: Simulation of The Power Rectifier with Capacitive Filter: Using Multisim or PSPICE, setup the Circuit in Figure 1. Specify the turn ratio of the Transformer to the Value that you have calculated. Using the Value of C1 and R1, Simulate your design. Print both the schematic and the transient plot of the circuit both with your name as a text label on it. 2 Miami Dade College Spring 2024---EET 1141C Step 4: Design the Zener Regulator Circuit V2 R5 1kQ Figure 2 D1 1N4733A Exam 1 R4 50 % 80%xPmax Vz0 RLoad_Min2 To Be Concluded in 3 Hours Using the Manufacturer Data Sheet supplied to you; Lookup the Manufacturer specification of the Zener Diode D1N4733A, that is available to you in Lab kit. Record down the following ratings at 25 degrees Celsius. Max Power Rating, Pmax; Typical Zener Voltage, Vzo: Typical Zener Impedance Zz: Zener Knee Current, Iz, knee:_ Maximum allowable Zener current, Iz,max= Although I had specified an R5 value of 1KQ; this is by no means the optimal Value to Use. You must design and choose your own value for R5. Since your Zener Regulator circuit will be coupled with your Capacitor-Filtered Rectifier Circuit, Use a V2 Value such that Vimin < V2< Vfmax, as your DC Voltage source in this independent Zener Regulator design. Design R5 such that, (1) The Zener with never exceed Iz, max calculated above and (2) even for no load (Open circuit Load); the current through the Zener will be below Iz,max but at the same time your Specification for the Line Regulation could be met. Show your design calculation below. R5 min = Value of R5 Such that your Line Regulation Specification will be Met = Practical Choice of R5=_ Next Calculate the No-load Current value of the Zener and Verify that it is below the maximum allowable Zener Current. Show your calculations below: Miami Dade College Spring 2024---EET 1141C IZNL:_ Using this Current, Calculate the No Load Voltage VNL: Next calculate the minimum load resistance Exam 1 To Be Concluded in 3 Hours RL,MIN: Practical Choice of RL,MIN=_ Replace the Load Resistor with two Resistors in series. (1) Your Choice of RL,MIN and (2) a 100KQ Potentiometer. This will ensure that while turning the potentiometer, your Total Load Resistance Varies from a minimum of RL,MIN to a maximum 100K+ RL,MIN. 4 Miami Dade College Spring 2024---EET 1141C Step 5: Simulating the Zener Voltage Regulator Setup the circuit in Multisim or PSPICE and Simulate the Circuit while Keeping the Load Resistance Constan at RL,MIN but Varying the Voltage source V2 from. Record your results in the Table Below. Line Regulation Test V2 Vfmin 0.5(Vfmin + Vfmax) Vfmax Using the Result in the Table above, Calculate the Load Regulation. Line Regulation How does Your Line Regulation measure up with your specification? = R4 RL,MIN Zener Current 0.5(100K+ RL,MIN) Exam 1 100K+ RL,MIN. Next Keep the Voltage Source V2 Constant at 0.5(Vfmin + Vfmax) and Vary the Load Resistance from RL,MIN to a maximum 100K + RL,MIN. Record your Simulation Measurements in the in table below. Load Regulation Test Zener Current Load Current Load Current To Be Concluded in 3 Hours Load Voltage Load Voltage Using Your Result in the Table above, Calculate the Load Regulation for the Zener Regulator You just designed.See Answer
  • Q15:EXPERIMENT 1 IT = 7.12 =?? NMB12303 ELECTRICAL ENGINEERING E 4 50V 1KHz ZT=V=5040/7.124-29 V₁ = 48.44-54.4 Power factor= cos 29= ?? lagging Ic V₂ R1 7.500 C1 Perform the experiment below: a) Measure the current I and deduce the Equivalent Impedance (Zr) viewed from the source voltage E. Also deduce the power factor. 4 -29° A 10.0 V₂ I 42 L1 1mH b) Measure All voltages (V₁, V₂) and currents (le, Ic, I). Put them in snapshots. Deduce their numerical values. Snapshot 1:E, V1 & V2 Snapshot 2: I, Ic, Is/nb) Measure All voltages (V₁, V₂) and currents (le, Ic, I). Put them in snapshots. Deduce their numerical values. Snapshot 1:E, V1 & V2 Snapshot 2: I, I, I V₁ = 48.44-54.4 V.= mag 461 Iz= mag angle Ic= mag Zangle = mag 4-29 c) Verify that voltage makes 90° angle with current in capacitor and inductor. Snapshot 3: V1 & k Snapshot 4: V2 & IL d) Verify that voltage is in phase with current in resistor. Snapshot 5: V1 & I e) Verify that the main voltage, E and main current I, makes less than 90° when there is combination of resistor, capacitor and inductor. Snapshot 6: E & ITSee Answer
  • Q16:DELIVERABLES: Need to create a power supply schematic in Multisim to feed a microcontroller ESp432 and other devices. Basically, we need to Desing a power supply schematic so it can feed everything using one singles or two batteries.See Answer
  • Q17:I. II. III. Part I: Objectives: After completing this lab experiment, you should be able to: • Measure the resistance and capacitance. • Familiarize with Oscilloscope and Function generator. • Measure the RC time constant using VR and Vc. Understand the effect of series and parallel capacitors on RC time constant. Parts List: • Resistor (1) 1 k Electric Circuits Lab Capacitors in DC Circuits Capacitors (2) 0.22 μF Procedures: 1. Construct the circuit shown in Figure 1 in Mutism. ru V1 100Hz 5V R1 m 1kQ Figure 1: Series RC Circuit C1 0.22μF 2. Connect Channel A of the oscilloscope across the voltage source and Channel B across the capacitor./n3. Set the function generator to 5V ppi 100 Hz, Square Wave 50% duty cycle with 2.5 DC offset if using a function generator. If using clock voltage, set it to 5Vpp, 100 Hz. The DC offset can be modeled by using DC mode on the oscilloscope. 4. Observe the signals on the scope screen. See Figure 2(a) below. (Use Volts/Div and Time/DIV settings to adjust the signal) Figure 2(a): Voltage across the Voltage Source and the capacitor 5. Disable Channel A, by setting it to 0, while observing Channel B. You should be able to see the waveform as shown below. Use time base and Channel A scale to adjust the signal. Figure 2(b): Voltage across the capacitor/n6. Change the time base (Sec/Div) until you have a clear waveform on the scope as shown in Figure 2(c). 7. Calculate the time constant of the RC circuit using the circuit parameter values. Record the result in Table 1 under calculated value. T=R*C Time constant (t) Figure 2(c): Voltage across the capacitor Calculated value 8. Measuring the time constant with Vc: V. Measured value using Vc Measured value using VR Table 1: Calculated and measured values i. Measure the peak value of the signal, by placing one of the cursors (T1) at the peak point ii. Calculate the 63% of the above value III. Place the second cursor (T2) at the step (ii) value above and T1 at zero just before the capacitor voltage starts rising as shown in Figure 3. iv. Observe the value of T2-T1 on the scope, which is the one time constant, as shown below. Record the result in Table 1 above under measured value using Vc./nFigure 5: Measuring RC time constant using Vc 9. Connect Channel B of the oscilloscope across the resistor. 10. You should be able to see the waveform as shown below. (Use Volts/Div and Time/DIV knobs to adjust the signal) Figure 6(a): Voltage across the resistor 11. Measuring the time constant with VR: i. Measure the peak value of the signal, by placing one of the cursors (T1) at the peak point Calculate the 27% of the above value/niv. V. Part II: Place the second cursor (T2) at the step (ii) value above. Observe the T2-T1 value on the scope, which is the one time constant. Record the result in Table 1 under measured value using VR. Figure 6(b): Measuring RC time-constant using VR 12. Place two capacitors in series as shown in Figure 7 below. C₁1 HH 0.22μF Capacitance C2 HH 0.22μF 13. Calculate the total capacitance value and record the results in Table 2 below. 1 G=1 +4₂ Figure 7: Series Capacitors Calculated Value Table 2: Series Capacitors Measured Value/n14. Measure the total capacitance value. Use the following procedure to measure the capacitance in Multisim. i. ii. iii. Connect the impedance Meter (Simulate>>Instruments>>LabView Instruments>>Impedance Meter) as shown in Figure 8. Measure the capacitive reactance, Xc, as shown in Figure 8. Calculate the capacitance using the equation, C = and record the value in 2nJXc Table 2. C1 HH 0.22μF C2 HH 0.22μF Figure 8: Impedance Meter in Multisim 15. Modify the circuit as shown below, by placing two 0.22μF capacitors in series as in Figure 8. C1 HH 0.22μF Time constant (t) V1 100Hz 5V C2 HH 0.22μF XLVI R1 >1kQ Ω Figure 8: RC circuit with two series capacitors Calculated value 16. Calculate the new RC time constant using measured values. Record the result in Table 3 below. Measured value using VR/nTable 3: Calculated and measured values 17. Connect Channel A of the oscilloscope across the resistor 18. Adjust the trigger if needed, and you should be able to see the waveform as shown in Figure 9 below. Part III: Figure 9: Voltage Across the Resistor 19. Repeat step 11. Record the measured time constant in Table 3 above. 20. Place two capacitors in parallel as shown in Figure 10 below. (Note: The 0.001 resistor is ONLY required for simulation in Multisim. Without the resistor, the mathematical model will not converge)./nii. R1 20.0010 III. C1 HH 0.22μF 21. Calculate the total capacitance value and record the results in Table 4 below. Capacitance C2 HH 0.22μF Figure 10: Parallel Capacitors CT = C₁ + C₂ Calculated Value Table 4: Parallel Capacitors 22. Measure the total capacitance value. Use the following procedure to measure the capacitance in Multisim. i. Measured Value Connect the impedance Meter (Simulate>>Instruments>>LabView Instruments>>Impedance Meter). Measure the capacitive reactance. Calculate the capacitance using the equation, C = Table 4. 1 2mfXc and record the value in 23. Modify the circuit by placing two 0.22μF capacitors in parallel as in Figure 11./nV1 100Hz SV 5 HH 0.22μF C2 HH 0.22μF R2 1kQ Figure 11: RC Circuit with Parallel Capacitors 24. Calculate the new RC time constant using measured values. Record the result in Table 5 below. 25. Connect Channel A of the oscilloscope across the resistor. 26. You should be able to see the waveform as in Figure 12 below. (Use Volts/Div and Time/DIV knobs to adjust the signal) 27. Use the cursors on the oscilloscope to measure the time constant (refer to step 11). Record the result in Table 5 below under measured value. Figure 12: Voltage across the resistor/nTime constant (t) Calculated value Measured value using VR Table 5: Calculated and measured values 10See Answer
  • Q18:I. II. III. Electric Circuits Lab Series RC Circuits: Phase Angle, Phase Lag, and Capacitors as Integrators Part 1: Objectives: After completing this lab experiment using, you should be able to: 1. Understand the effect of frequency on capacitive reactance. 2. Measure the impedance of an RC circuit. 3. Measure the phase angle and phase lag of an RC circuit using the oscilloscope. 4. Draw the impedance and voltage phasor diagrams 5. Understand how a capacitor integrates current. Parts List: 1. Resistor 1000, 1k, 6.8 k 2. Capacitors 0.1 µF, 0.01 µF Procedures: 1. Connect the following circuit. VS 1Vrms 1 kHz R1 ww 1.0k Figure 1: RC Circuit 1 C1 =0.1pF 2. Connect one DMM across the resistor and one DMM across the capacitor. Set both DMM sto read AC voltage. Measure the voltage drop across each component. Record the result in Table 1./n3. Use Ohm's law to calculate the current flowing through the resistor. Since the circuit in Figure 1 is a series RC circuit, the same current will flow through the capacitor and the resistor. Record the result in Table 1. 4. Calculate the capacitive reactance using Ohm's law. Record the result in Table 2. Vc Capacitive Reactance, Xc = I Total current, I = R 5. Now, calculate the capacitive reactance value using the equation below. Record the result in Table 1 under Computed Reactance, Xc. Capacitive Reactance, Xc = Frequency (in Hz) 300 1k Voltage across, R Voltage across, C Total Current, I Capacitive Reactance, Xc Computed Reactance, Xc 6. Adjust the function generator frequency following the steps in Table 2. Use the DMM to measure the voltage across the resistor and the capacitor. Record your measurements below. 1 2nfC Table 1: Calculated and measured values VR Vc (measured) (measured) Capacitor C₁ 2 VR 1 = R Xe= I (calculated) (calculated) Vc 1 (2nfc) (calculated) Xc=/n3k 5k 7k 9k 11k 13k 15k Table 2: Calculated and measured values 7. Plot the graph for Frequency vs. Vc. (Use Excel or Word to Create the Plot) Plot 1: Frequency vs. Vc Part II: 8. Build the circuit shown in Figure 2. 1.5Vpk 500Hz 0 Vs C1 HH 0.01 μF R1 6.8kQ Figure 2: Series RC Circuit 3 9. Set the source voltage amplitude to 1.5 V, and frequency to 500 Hz./n10. Connect Channel A of the oscilloscope across the resistor and measure the peak voltage drop (VR). Record the result in Table 3. 11. Use Ohm's law to calculate the peak current flowing through the resistor. Because it is a series circuit, the same current will flow through the capacitor. Record the result in Table 3. VR I Total current = R Vc Xc Z₁ Table 3: Calculated and measured values 12. Connect Channel B of the oscilloscope across the capacitor and measure the peak voltage drop (Vc). Record the value in Table 3. 13. Calculate the capacitive reactance using Ohm's law. Record the result in Table 3. Vc Capacitive Reactance Xc = 7 e Vs Total Impedance (ZT) = Ť 14. Now, calculate the total impedance (Z₁) value using the equation below. Record the result in Table 3. 15. Calculate the phase angle between VR and Vs using the formula below. Record the result in Table 3. Also, record this value in Table 4 under Phase Angle calculated value. Phase angle, 8 = -tan-¹ (*) Part III: Phase Angle and Phase Lag Measurement Phase Angle 16. Connect Channel A of the oscilloscope across the resistor and Channel B of the oscilloscope across the function generator and run the simulation. 17. The waveforms should look like the ones shown in Figure 4./nMAAAA Vs VR Figure 4: Vs and VR waveforms 18. Obtain a stable display showing a couple of cycles for Channel B (which is showing Vs) and disable Channel A by setting it to 0. 19. Measure the time period (T) of the source voltage. Record the result in Table 4 below. (Use the cursors to measure the period (on the scope it will show as T2-T1). Remember that the period is the time taken to complete one cycle). See Figure 5. Figure 5: Measuring time period (T) 5/nType of Angle Phase angle 8 Phase Lag Measured Period (T) Time difference Measured (At) Angle Table 4: Phase angle and phase lag measurements 20. Now set the oscilloscope to view both the channels. 21. Adjust the amplitude of the signals using Channel A and Channel B V/Div scale until both channels appear to have the same amplitude as seen on the scope face. (as close as possible) Phase Lag 22. Spread the signals horizontally using the Timebase (Sec/Div) control until both signals are just visible across the screen as shown below. Calculated Angle 23. Measure the time duration between the two signals (At) and record the result in Table 4 above. (Use cursors as shown below in Figure 6) Figure 6: Measuring the time difference 24. Calculate the phase angle using the formula below and record the result in Table 4. Phase angle, 8 = (At/T)* 360°/nlag circuit will lag the input voltage. 1.5Vpk ~500Hz 0" Vs R2 6.8kQ C2 =0.01 μF Figure 7: RC Lag Circuit XSC2 26. Calculate the phase lag using the equation below. Notice the similarity to the equation for the phase angle. The phase lag angle and phase angle of an RC circuit are complementary angles. (Their sum is 90°.) Use R and Xc values from Table 3. Phase Lag, ø = tan-¹) 27. Measure the time period (T) of the source voltage (as in Step 19). Record this value in Table 4. 28. Now set the oscilloscope to view both the channels. 29. Adjust the amplitude of the signals using Channel A and Channel B V/Div scale until both channels appear to have the same amplitude as seen on the scope face. (as close as possible) 7 30. Spread the signals horizontally using the Timebase (Sec/Div) control until both signals are just visible across the screen as shown in Figure 6. 31. Measure the time duration between the two signals (At) and record the result in Table 4 above. 32. Calculate the phase lag using the formula below and record the result in Table 4. Phase lag, Ø = (At/T) * 360°/n33. Plot the Voltage and Impedance Phasor Diagrams. Clearly indicate the phase angle and the phase lag. Measure the peak voltages for VR and Vc with the oscilloscope. (Use Excel or Word to create diagrams) Plot 2(a) Impedance Phasor Plot 2(b) Voltage Phasor Part IV: The Capacitor Integrates Current 34. Construct the following RC circuit in Multisim. Set the clock voltage source to 10 kHz, 10V, 50% duty cycle./nru ru V1 10kHz 10V V1 10kHz 10V Figure 9. Integrator Circuit 35. Connect Channel A across the resistor and Channel B across the capacitor. (Note: change one or both trace colors to better observe the two signals) R1 3kQ R1 mw 3kQ C1 5.6μF C1 5.6μF Figure 9a. Integrator Circuit with Oscilloscope Connections ET 36. Run the simulation. Your signals should look like the example in Figure 9b./nOscilloscope-XSC1 T2 T2-T1 VR Vc Time 164.481 ms 164.481 ms 0.000 s Timebase Scale: 20 us/Div X pos.(Div): 0 Y/T Add B/A A/B Channel A -4.999 V -4.999 V 0.000 V Channel B -1.675 mV -1.675 mV 0.000 V Channel A Scale: 2 V/Div Y pos.(Div): 0 AC O DC Figure 9b: Capacitor as an integrator waveforms Channel B Scale: 5 mV/Div Y pos.(Div): 0 OAC 0 DC- v(t) >= ²1 [₁ v(t) = ½ ju(t)dr {=C 37. Channel A will show the voltage across the resistor. This signal can be used to find the circuit current using Ohm's law. 38. Channel B shows the voltage across the capacitor. Show that this signal satisfies the following equation. We will do this in intervals in the following steps. dv dt i(t)dr Reverse = - 1/1(1) Save t(t)dt + + Ext. trigger Trigger Edge: A B Ext Level: 0 O Single Normal Auto None t(r)dr/nT2 T2-T1 39. Refer to Figure 10 to answer the following questions. Oscilloscope-XSC1 Time 164.100 ms 164.150 ms 50.001 us v(0) = 1 ju(r)dr v(t): 1) = ²½ [167)ar = √ [ 16 [1(r)dr Timebase Scale: 20 us/Div X pos.(Div): 0 Y/T Add B/A A/B Channel A -1.993 V 1.992 V 3.985 V Channel A Scale: 2 V/Div Y pos.(Div): 0 AC O DC Channel B -7.425 mV 14.882 mV Channel B Scale: 5 mV/Div Y pos.(Div): 0 O AC O DC Figure 10: Integrator values, 0 to 50 µs i(t): 11 1(T)dt + v(0) t=50μS = mVys a. The signal has a period of 100 us. Write the equation for the circuit current on the interval 0 to 50 us. On the interval of 0 to 50 µs, va(t) is constant so the current will be constant as well. VR(t) R Reverse Save Ext. trigger Trigger Edge: A B Ext Level: 0 V Single Normal Auto None/nb. Write the equation for the voltage across the capacitor by solving the integral. You will need to read the value vc(0) from Figure 10. 50 μ v(t) = [1(x)dx+v(0) c. Confirm your equation by predicting the value of vc(50 µs). d. Read the value of vc(50 us) from Figure 10. 40. Refer to Figure 11 to answer the following questions. Oscilloscope-XSC1 T2 T2-T1 t=50μs Time 164.400 ms 164.450 ms 50.001 us Timebase Scale: 20 us/Div X pos.(Div): 0 Y/T Add B/A A/B Channel A -1.993 V 1.992 V 3.985 V Channel A Scale: 2 V/Div Y pos.(Div): 0 AC O DC t=100μs 12 Channel B -7.424 mV 7.457 mV 14.882 mV Channel B Scale: 5 mV/Div Y pos.(Div): 0 AC 0 DC Figure 11: Integrator values, 50 to 100 μs X Ext. trigger Reverse Save Trigger Edge: A B Ext Level: 0 V Single Normal Auto None/na. The signal has a period of 100 us. Write the equation for the circuit current on the interval 50 µs to 100 µs. On the interval of 50 to 100 μs, vr(t) is constant so the current will be constant as well. i(t) = VR(t) R b. Write the equation for the voltage across the capacitor by solving the integral. You will need to read the value vc(50) from Figure 11. v(t) = 11(x) + (50) 50 μs c. Confirm your equation by predicting the value of vc(100 µs). d. Read the value of vc(100 us) from Figure 11.See Answer
  • Q19:2. (Ripple in a power supply) Set up the following circuit: V1 230Vrms 50Hz 0° F www. www 25:1 D1 184842 DE +₁ C1 200μF a. Use an oscilloscope to measure the peak-to-peak ripple voltage in the load. Is it as you would expect? b. Change the capacitance to 100 μF and 300 μF, and measure the peak-to-peak ripple in both cases. Plot the ripple voltage as a function of 1/C, apply a linear fit and comment on the value of the slope c. Double the load DC voltage by (i) changing the turns ratio, (ii) inserting a clamper between the transformer and rectifier R1 5KQ thSee Answer
  • Q20:Part B: CD4538 Monostable (Simulation) 3. Using a CD4538 and design a retriggerable monostable with the pulse width of 1ms. Suppose the power supply is +5V. Use a 200 Hz, 0/+5V pulse as the trigger signal. Simulate the circuit, use the oscilloscope tool to observe the input and output voltages simultaneously. Complete the following table. Parameter VOUT, High Voltage Level VOUT, Low Voltage Level VOUT, Pulse Width Value Review the simulation results, and verify the pulse width, adjust the circuit if required. Attach the circuit schematic to the lab report.See Answer
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