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Expert help when you need it- Q1:Design a 64*64 Sram array block. Each array block has 8 WL. I need total four such blocks. The arrangement should be such that the control block should be in the middle of the 4 blocks. Control block contains pre-decoder, decoder. The final output should be of 128 bits. Please provide diagram with all the above details along with peripheral circuits such as write drivers, pre charger circuits, sense amplifiers, output latches and FF, column mux and any other parts necessary. Please provide the individual sizes and configurations of each circuit block used.See Answer
- Q2:2. Using the structural approach, write the VHDL code to implement a full adder. The schematic of a full adder is illustrated in figure 9. Make sure to declare all the necessary components, including the OR2 gate. Compile and simulate your design. As you did in 1), create a VHDL component from the current file. Make sure to log your results - Screenshots of both the VHDL code and simulation. Halfadder AB Α A AB C SS Halfadder A с B S S Cin Figure 9: Full Adder using two half adders Cout -SumSee Answer
- Q3:1) Design using VHDL with EDA Playground, a 4 x 4-bit parallel multiplier using the correct number of adder blocks full-adders (FAs) and half-adders (HA). This must include the AND gates to generate the product terms and use the carry-save method with a ripple-carry adder in the final row (CLA adder is not required in the last row). a. You would need to use the RTL level design for the basic gates, i.e., AND, OR, XOR, etc. gates. Then, FAs and HAs need to be implemented using the structural (or logic gate) level design. Finally, the final parallel adder requires the structural (or logic gate) level design for connecting the AND gates, FAS and HAS. b. Per each of the basic gates, consider the delay based on the architecture, i.e., AND gates delay; c. Show simulation results by designing a dedicated testbench (i.e., testbench.vhd) and using Open EPWave with different input values in the range of 0-15. d. You should explain in a short report the design process and choices (up to 2 pages max).See Answer
- Q4:Problem 1. NMOS large-signal model (Gray: 1.15) For a NMOS transistor (A = 0.1V-¹): (a) Sketch the ID vs VDs characteristics for VDs from 0V to 3V and VGs = 0.5V and 1.5V. Assume VSB OV. (b) Sketch the ID vs VGs characteristics for VDS 2V and VGS from 0V to 3V. Assume VSBOV and 1V.See Answer
- Q5:Problem 1. NMOS large-signal model (Gray: 1.15) For a NMOS transistor (A = 0.1V-¹): (a) Sketch the ID vs VDs characteristics for VDs from 0V to 3V and VGs = 0.5V and 1.5V. = OV. Assume VSB (b) Sketch the ID vs VGs characteristics for VDS 2V and VGS from 0V to 3V. Assume VSBOV and 1V.See Answer
- Q6:Problem 1. Output resistance and small signal gain: 30 points (Razavi) Assume Ip is 1 mA, y = 0, L = 0.5μm and ()₁ = ()₂ = (H)3 = 100, calculate small-signal gain and output resistance for the circuits in Fig. 1 thru 3.See Answer
- Q7:Problem 2. Maximum output swing and bias: 20 points In Fig. 2 and 3, assuming same device size as in Problem 1 and VDD = 3V, calculate (a) Nominal bias voltages (V61, V62) assuming ID = 1mA. (b) Maximum and minimum values of Vout such that all devices are in saturationSee Answer
- Q8: a)Explain in no more than 300 words the difference between the large and the small signal models for a Bipolar Junction Transistor (BJT). Explain why the operating point in l-V characteristics of BJT plays a central role in determination of a signal model. Can this determination be done without the operating point? b)Draw a schematic of the p-n-p Bipolar Junction Transistor (BJT) fabricated on a silicon substrate as a part of an integrated circuit. Explain your choice of the particularly doped silicon substrate and the order of fabrication steps in an eventual fabrication flow for the p-n-p BJT. Draw a schematic of so-called Cascode Amplifier and explain how this configuration is related to the three circuit configurations (namely a common-base, a common-emitter,and a common-collector) for a Bipolar Junction Transistor (BJT) to act as an amplifier.Write a comparison of the Cascode Amplifier configuration with respect to the three common configurations with respect to: the voltage gain, the current gain, and the power gain.(6 marks7 d)Describe three applications of the Bipolar-CMOS-DMOS (BCD) power transistor of your choice in a custom chip. Write an essay of no longer than 300 words justifying why the BCD power transistor is an optimal solution for each of the three chip applications selected.See Answer
- Q9: a)Describe in an essay no longer than 400 words your own understanding of a validity of Moore's Law for the digital CMOS transistor scaling. Address the following issues:the dimensions of transistors, the density of transistors, the operational frequency of transistors, the design of digital circuits made of the transistors, the number of cores in a processor, and the cost of the transistors related to the cost of fabrication and to the cost of a technology development. b)Find at least four technology innovations which had to be introduced into the technology nodes to boost a performance of CMOS transistors in order to meet requirements for digital circuits and thus continue the scaling. Write a maximum of 300words essay to explain the technical reasons for your selected technology innovation.Justify that your technology chosen change is an innovation.18 marksl c)MOSFET which has a conduction parameter of 50 mAN? and a threshold voltage of0.5 V. If the supply voltage is +15 Vand the load resistor is 365 Q, calculate the values of the resistors required to bias the MOSFET amplifier at 1/3 (VDD).A common source MOSFET amplifier is to be constructed using an n-channel d)How is a gain (A) in a MOSFET based amplifier related to the input resistance (RIN)and the output resistance (RouT) ?1 morl1See Answer
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