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  • Q1:Level 1 - Design of a simple parallel Input/Output One of the most common I/O subsystems is the parallel input or output which uses a simple n-bit register for storing the output and another one for storing the input. This is very often called latched I/O, and uses the following structure: UFMFQT-15-2 UFMFQT-15-2 from outside ↓ to registers Digital System Design Digital System Design Implement the above shown structure in VHDL Simulate your design and show correct behaviour from registers Your submission must include the following: ↓ Two 8bit registers are used in this case. The clock signal on the right structure is controlled by the executioner, while the clock signal of the left structure is controlled by the outside environment. Therefore, even short signal changes can be stored in the Input Structure (left), since the values are stored in the register. Your task is to: to outside All VHDL sources • Screenshots of the simulation showing correct behaviour 2 3See Answer
  • Q2:Level 2 - Design of an 8bit+8bit BCD Adder You task is to design an BCD adder, that adds two two-digit BCD numbers. The structure of a 4bit BCD adder is as follows: Your submission must include the following: Design your BCD adder in VHDL; this must be structural for the top-level Simulate your design and show correct behaviour; the input and output vectors must be shown in decimal . ALL VHDL sources . carry out All simulation screenshots Sum> 97 carry out binary adder binary. adder Sum 0 carry inSee Answer
  • Q3:USe Xilinx Vivado to design and simulate the logic shown. Inputs A, B, C, D are 4-bit wide. Make sure you test your design for all the operations listed above. Submit vhdl code, RTL schematic, screenshots of simulation waveforms, , and test bench of the design. Test your design using at least five test cases. Mark two of the test cases and show the corresponding inputs, expected outputs and simulated outputs for those two cases. The source files should contain appropriate comments for better understanding.See Answer

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