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Q1: Figure A5 shows a cascade of multiplexers. When S is logic-0, the output Y is driven by the upper input (0), and when S is logic-1 the output is driven by the lower input(1). Write down an equivalent Verilog continuous assignment for Fig. A5. See Answer
Q2: A2Write down the value for signalY', given A = 8'b11110111 and the following Verilog continuous assignment: See Answer
Q3: Given the following two values: Y = 8'b10010111 H =8 b10101010 Write down the result of the following assignment: See Answer
Q4: Figure B3a shows a data exchange system that uses a single-bit shared bus line(SB) to pass digital information from a set of data transmitters, 'AQA3 and CO..C3',to data receivers 'B0..B3 and DO.D3'. All signals are 1-bit, apart from SA, SB, SCand SD, which are 2-bit (indicated by the 'x' enclosed within the terminal symbols). The two multiplexers (MUXS) at top-left and bottom-right of Fig. B3a use 2-bit select inputs 'SA' and 'SC' to choose a transmit channel (03). Similarly, the two de-multiplexers (DMXS) at top-right and bottom-left of Fig. B3a use 2-bit select inputs"SB' and 'SD' to choose a receive channel (03). Choose either the MUX or DMX and sketch a gate-level logic circuit implementation of the symbol (MUX or DMX). Depending upon which choice you made above, write down the Verilog-HDL description of the other symbol, Le if you sketched the logic circuit for the MUX (DMX), write down the Verilog description of the DMX (MUX). In your descriptions, you may make use of continuous assignment statements and/or primitive gate instantiations.(6 morke) Write down the name of the Verilog-HDL built-in primitive element that could be used to model the four three-state buffers connected to the shared bus 'SB', in Fig. B3a. Write down the values, in Verilog format, of the following control signals: SA, SB, SC, SD, ENA and ENB In order to perform the following data transfer operations in Fig. B3a: i.Transmit data from A3 to B1. Figure B3b shows a particular type of counter based on a shift register. The asynchronous set (S) and reset (R) inputs of the flip-flops are active-high, assume any unconnected inputs are at logic-0. (2 marks)Sketch a set of digital waveforms for the outputs, <Q3, Q2, Q1, Q0>, of the counteralong with the clock input 'CIK. Assume the circuit has previously been reset bypulsing the Rst input to logic-1. (6 marks)Given that the frequency of the clock input 'Çlk' is 10 MHz, deduce the frequency of any Q output.See Answer
Q5: With reference to Fig. A8, write down the name of the Verilog-HDL primitive element for components labelled 'T1' and T2'.See Answer
Q6: Referring to Fig. A19, write down a pair of input combinations, which if applied to the logic circuit inputs in sequence, would reveal the timing hazard.See Answer
Q7: Figure A19 shows the K-Map of a sum-of-products logic circuit showing thegroupings used to form the products. Write down the type of static hazard present in the sum-of-products circuit.See Answer
Q8: 5. Use a synchronous 4-bit binary up counter (with load and enable) to design a modulo-8counter (also called offset counter) that begins with 0100, which means the counting sequence is: 0100->0101->0110->0111->1000->1001->1010->1011->0100-0101... Please complete your design using the figure need. on the next page. Use some logic gates if you need See Answer
Q9: (Q.2) Tiny Power System, that you developed in Assignment 1 has a control center and 3 substations, all of them connected through the SCADA system. Although the system is small, all 3 substations are installed with an Intelligent Electronic Device (IED). Each substation has 2 circuit breakers on the 2 transmission lines connecting the other 2 substations.Develop a detailed model of the cyber system deployed on the Tiny Power system using a software tool (similar to the ICT models described in [1]). Describe your model in a 2-page report. Specify sources of cyber vulnerabilities and explain how your model can be used for simulation of the impact of cyber attacks.See Answer
Q10: Pre-scaling by 8 means the configuration register of the timer will be divided into 8 bits the counting frequency of the timer will be divided by 8 the counting frequency of the timer will be multiplied the maximum count of the timer will be multiplied by 8.See Answer
Q11: 3. T flip - flop T flip-flop works as follows: if the input T = 0, the output stays the same; if the input T =1,the output toggles. In other words, the characteristic equation for the T flip-flop is Q+= TOQ. a) Complete the following state transition table for the T flip-flop. b) Complete the following timing diagram for the T flip-flop. Assuming Q=0 at the beginning. See Answer
Q12: Explain the characterestic curve of a Varistor(Minimum 5 sentences) shown below. ReferTrg Notes Page No-32 See Answer
Q13: QUESTION 6Design a minimum three-level NOR-gate circuit to realize f = a'b' + abd + acdSee Answer
Q14: 3. We discussed in class about electromagnetic interference and performed related experiments in our lab. Suppose you are designing a medical device to acquire a bio signal that has frequency components between 1 and 500 Hz. The device will be used in an environment that is susceptible to a very high 60 Hz electromagnetic interference. What is your approach to minimize the interference without distorting the bio signal been measured? You must explain your answer. (20 pts) Be specific, clear, direct and succinct in your questions.See Answer
Q15: V a) Compute the sheet resistance of a 0.2 micron thick aluminum wire with resistivity 0.02 micro ohm.m. Find the resistance of the wire if it is 0.2 micron wide and 1 mm length. b) What is the parallel plate capacitance of wire if it is isolated from substrate with oxide thickness 0.2 micron. c) Why we have to use low dielectric constant materials for isolating interconnects. c) Why we have to use low dielectric constant materials for isolating interconnects. d) Find the interconnect delay for the above interconnect. d) Determine the skin depth for the above wire for pulse propagating with an of 30 psec.edge rate e) Does the interconnect delay depend on temperature? Does it increases or decreases with increase in temperature.See Answer
Q16: 2. (17 points) The purpose of this problem is to explore one use of the voltage-dependent depletion capacitance of a diode. Consider the schematic shown here for the front end of a simple radio with an antenna near the top of the diagram in Figure 3-2 and connected to a tunable tank circuit.. Let R1 = 75 N and the inductor's value be L= (1000+X 31D) nH. The silicon diode has a pn junction area of 40 µm × 50 um^2, with both sides doped relatively heavily at NA-ND=1018 cm³. Assume Is = 1 pA. (a) What is the built-in voltage of the diode? (See Razavi's Eq. 2.69.) (b) What is the zero-bias depletion capacitance of the diode? (See Razavi's Eq. 2.76.) (c) What is the resonant frequency of the tank circuit if the diode is not biased? (d) If you want to tune the radio to KCSU-FM, what should be the voltage of V tune?[Note that there is a sign error (or labeling error) in Razavi’s Eq. 2.75. There is no positive reverse voltage (VR =-That equation should have read VD) that can make the capacitance approach infinity. C_{\text {depl }}=\frac{C_{0}}{\sqrt{1+\frac{V_{R}}{V_{b i}}}} See, for example, that the corrected equation is used in Example 2.15 in Eq. 2.82.]See Answer
Q17: Let X(2) be a causal LTI system with its poles and zeros located in the unit circle. Further,assume that the ROC includes the unit circle. We can express this system generically as: X(z)=A \frac{\prod_{k=1}^{M_{1}}\left(1-\alpha_{k} z^{-1}\right)}{\prod_{k=1}^{N_{1}}\left(1-\gamma_{k} z^{-1}\right)} where M1 are the number of zeros and and N1 are the number of zeros. You can assumethat for complex conjugate zeros (poles) that ak = a; (7k = V;). The Cepstrum is definedas C_{x}(z)=\log X(z) Using the information above, find c[n] (i.e., the time domain sequence for C(2)). Hints • You only need to find c[n] for n > 0. It might be helpful to have your Maclaurin series look-up tables nearby.See Answer
Q18: Q2. A common-source equivalent circuit is shown in Figure Q2. The transistor trans-conductance is gm = 3mA/V. a) Calculate the equivalent Miller Capacitance (6 points). b) Determine the upper 3dB frequency for the small-signal voltage gain (6 points). See Answer
Q19: Q6: The parameters of the transistors in Figure Q6 are Vtm = 0. 6 V, kn =100 µA/V2,V = -0.6 V, k, = 60 µA/V2, and lamda n = lambda p, = 0.02 V-1. The width-to-length ratios of transistors are shown in the figure. The value of Vasa is such that Ip1 = 100uA, and M1 and M2 are biased in the saturation region. Determinethe small signal voltage gain A, = vo/vm (12 points). See Answer
Q20: Q1. For the circuit shown in Figure Q2, the transistor parameters are: Kn=0.5 mA/V2, V en =2 V and = 0. a) Determine the maximum value of C, such that the bandwidth is 5 MHz. State any approximations or assumptions that you make (6 points), b) What is the magnitude of the small-signal mid-band voltage gain? (6 points), and c) verify your results using Multi-sim and CD4007 transistor model (gain and bandwidth) and explain any differences (4 points). See Answer

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