# basic electronics homework help

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• Q1: A2Write down the value for signalY', given A = 8'b11110111 and the following Verilog continuous assignment: See Answer
• Q2: Given the following two values: Y = 8'b10010111 H =8 b10101010 Write down the result of the following assignment: See Answer
• Q3: AT7Write down a bit pattern to apply to inputs <A, B, C, D, E, F> in order to transfer the"Data in source to the 'Data out destination (assume that 'S2' is the most significant bit for both the Mux and Demux) in Fig. A17. See Answer
• Q4: Referring to Fig. A19, write down a pair of input combinations, which if applied to the logic circuit inputs in sequence, would reveal the timing hazard.See Answer
• Q5: Figure B3a shows a data exchange system that uses a single-bit shared bus line(SB) to pass digital information from a set of data transmitters, 'AQA3 and CO..C3',to data receivers 'B0..B3 and DO.D3'. All signals are 1-bit, apart from SA, SB, SCand SD, which are 2-bit (indicated by the 'x' enclosed within the terminal symbols). The two multiplexers (MUXS) at top-left and bottom-right of Fig. B3a use 2-bit select inputs 'SA' and 'SC' to choose a transmit channel (03). Similarly, the two de-multiplexers (DMXS) at top-right and bottom-left of Fig. B3a use 2-bit select inputs"SB' and 'SD' to choose a receive channel (03). Choose either the MUX or DMX and sketch a gate-level logic circuit implementation of the symbol (MUX or DMX). Depending upon which choice you made above, write down the Verilog-HDL description of the other symbol, Le if you sketched the logic circuit for the MUX (DMX), write down the Verilog description of the DMX (MUX). In your descriptions, you may make use of continuous assignment statements and/or primitive gate instantiations.(6 morke) Write down the name of the Verilog-HDL built-in primitive element that could be used to model the four three-state buffers connected to the shared bus 'SB', in Fig. B3a. Write down the values, in Verilog format, of the following control signals: SA, SB, SC, SD, ENA and ENB In order to perform the following data transfer operations in Fig. B3a: i.Transmit data from A3 to B1. Figure B3b shows a particular type of counter based on a shift register. The asynchronous set (S) and reset (R) inputs of the flip-flops are active-high, assume any unconnected inputs are at logic-0. (2 marks)Sketch a set of digital waveforms for the outputs, <Q3, Q2, Q1, Q0>, of the counteralong with the clock input 'CIK. Assume the circuit has previously been reset bypulsing the Rst input to logic-1. (6 marks)Given that the frequency of the clock input 'Çlk' is 10 MHz, deduce the frequency of any Q output.See Answer
• Q6: The following Verilog continuous assignment describes the logic of a circuit that has4 inputs '13, 12, 11 and 10' and 2 outputs 'Y1 and YO'. (All signals are 1-bit): See Answer
• Q7: A4In a Verilog-HDL source description, write down the name given to the following part of a source description: See Answer
• Q8: Figure A5 shows a cascade of multiplexers. When S is logic-0, the output Y is driven by the upper input (0), and when S is logic-1 the output is driven by the lower input(1). Write down an equivalent Verilog continuous assignment for Fig. A5. See Answer
• Q9: With reference to Fig. A8, write down the name of the Verilog-HDL primitive element for components labelled 'T1' and T2'.See Answer
• Q10: Figure A19 shows the K-Map of a sum-of-products logic circuit showing thegroupings used to form the products. Write down the type of static hazard present in the sum-of-products circuit.See Answer
• Q11: 5. Use a synchronous 4-bit binary up counter (with load and enable) to design a modulo-8counter (also called offset counter) that begins with 0100, which means the counting sequence is: 0100->0101->0110->0111->1000->1001->1010->1011->0100-0101... Please complete your design using the figure need. on the next page. Use some logic gates if you need See Answer
• Q12: What is the value of the cut-off frequency? \text { a. } 0.6 \mathrm{KHz}+/-0.1 \mathrm{KHz} \text { b. } 2.0 \mathrm{KHz}+/-0.1 \mathrm{KHz} \text { c. } 1.0 \mathrm{KHz}+/-0.1 \mathrm{KHz} \text { d. } 1.6 \mathrm{KHz}+/-0.1 \mathrm{KHz}See Answer
• Q13: Value of the phase shift, A(0) =? a. 1.56 +/- 0.1l rads b. delta(0) = 0.56 +/- 0.1 rads c. 5.60 +/-0.1 rads d. delta(0) = -0.56+/- 0.1 radsSee Answer
• Q14: Using the information in the background theory (next section in this handout), calculate the tir (a) R= 1KOhm, C = 100 nF (b) R=10 KOhm, C = 100 nF Select one: a. (a) 0.000001 (b) 0.01 b. (a) 0.0001 sec (b) 0.001 sec O c. (a) 0.00001 (b) 0.00001 O d. (a) 0.01 (b) 0.001See Answer
• Q15: Value of the capacitor's voltage amplitude Vc? a. 2 Sqrt(2) +/-0.2 volts b. 0.69 +/- 0.2 volts c. 1.69 +/- 0.2 volts d.0.5 +/-0.2 voltsSee Answer
• Q16: What is the difference of this amplitude and the amplitude for the small time constant? and why there is a difference?. V_{C}=0.31+/-0.05 \text { volts } Because the 10K ohm resistor decreases the current. \mathrm{V}_{\mathrm{C}}=0.31+/-0.05 \text { volts } Because the resistance of the capacitor changes with the frequency \text { c. } V_{C}=0.31+/-0.05 \text { volts } Because the time constant is as large as the frequency, hence the capacitor is never fully charged in the cycle. V_{C}=3.1+/-0.05 \text { volts } Because the time constant is as large as the frequency, hence the capacitor is fully charged in the cycle.See Answer
• Q17: (Q.2) Tiny Power System, that you developed in Assignment 1 has a control center and 3 substations, all of them connected through the SCADA system. Although the system is small, all 3 substations are installed with an Intelligent Electronic Device (IED). Each substation has 2 circuit breakers on the 2 transmission lines connecting the other 2 substations.Develop a detailed model of the cyber system deployed on the Tiny Power system using a software tool (similar to the ICT models described in [1]). Describe your model in a 2-page report. Specify sources of cyber vulnerabilities and explain how your model can be used for simulation of the impact of cyber attacks.See Answer
• Q18: (Q1) Prepare a short report about key differences between electrons flow in the electric grid(considering electrons will not cross transformers) and data packets flow in the SCADA system.Develop a table comparing source, sink, control devices, control mechanisms and protocols followed in these systems for electrons/ data packets?See Answer
• Q19: Pre-scaling by 8 means the configuration register of the timer will be divided into 8 bits the counting frequency of the timer will be divided by 8 the counting frequency of the timer will be multiplied the maximum count of the timer will be multiplied by 8.See Answer
• Q20: Explain the need for state minimization (2 marks) A synchronous, sequential system is represented by the state table below Minimize the state table using an implication chart . Hence, draw an equivalent, but minimal state table and the minimized state diagram|. See Answer

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