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Q1: Experiment 3: Logic Gates and Pull-Up and Pull-Down Resistors OJECTIVES After completing this experiment, you will be able to Experimentally verify the truth tables for the NAND and NOR, and inverter gates. Use the NAND and NOR gates to formulate other basic logic gates. MATERIALS NEEDED 7400 quad 2-input NAND gate 7402 quad 2-input NOR gate 7404 NOT gate (inverter) DMM probes THEORY LOGIC GATES Logic gates are the basic building blocks of digital electronic circuits. They are devices that perform a specific logic operation on one or more input signals and produce a single output signal. The most basic logic gates are the NOT gate, AND gate, OR gate, and XOR (exclusive OR) gate. These gates can be combined to create more complex circuits that perform more advanced logic operations. UNIVERSAL LOGIC GATES There are three types of logic gates that are considered to be "universal" because they can be combined to create any other logic gate or digital circuit. These universal gates are: NAND (NOT-AND) gate: This gate performs the opposite function of an AND gate, meaning it produces a low output (0) if all of its inputs are high, and a high output (1) otherwise. NOR (NOT-OR) gate: This gate performs the opposite function of an OR gate, meaning it produces a high output (1) if all of its inputs are low, and a low output (0) otherwise. NOT gate (inverter): As the name suggests, it inverts the input signal, so that a high input (1) produces a low output (0), and vice versa. Since NAND and NOR gates are universal gates, any logic circuit can be implemented using only NAND gates, or only NOR gates. TTL (TRANSISTOR-TRANSISTOR LOGIC) TTL (Transistor-Transistor Logic) is a type of digital logic circuit that uses transistors to switch between the two logic levels of 0 and 1. High = 1 Indeterminate Region Low=0 SV 3V 2.4V 2V IV 0.4V OV Figure 3. 1: TTL Switching Voltages 35 As shown in Figure 3.1, the logic HIGH or binary '1' level is typically represented by a voltage between 2.4V-5V, while the logic LOW or binary '0' level is represented by a voltage between OV-0.4V. The exact voltage levels may vary depending on the specific type of TTL circuit. HOW TO CREATE INPUT SIGNALS IN THE LAB Pull-down and pull-up resistors are used in electronic circuits to establish a known or defined voltage level when a switch is open. They are typically used in digital circuits to prevent floating or undefined states that could lead to unreliable or incorrect readings. +5.0V Table 3. 1 -OVout 1k, Pull-Down Switch State Open Closed Figure 3. 2 PULL-DOWN RESISTOR A pull-down resistor is connected between the signal line and ground. When the switch is open, the pull-down resistor ensures that the voltage is "pulled down" to a LOW level (e.g., 0 volts or ground). This establishes a clear "off" or "0" state for the signal. PULL-UP RESISTOR On the other hand, a pull-up resistor is connected between the signal line and a positive voltage source (e.g., Vcc or +5 volts). When the switch is open, the pull-up resistor "pulls" the voltage up to a high level (e.g., 5 volts). This establishes a clear "on" or "1" state for the signal. A When the switch is closed, the pull-down or pull-up resistor has little effect as the switch takes precedence and overrides the resistor's influence on the signal voltage level. +5.0V Pull-Down OV, '0' 5V, '1' 1k, Pull-Up A -OVout Vin Figure 3. 3 In digital circuits, it's important to have a well-defined voltage level to ensure reliable signal interpretation by the receiving circuitry (such as microcontrollers or logic gates). NAMING PORTS ON A SCHEMATIC To simplify the schematic, we can replace the entire pull-up or pull-down network with just the port. +5.0V Pull-Up 5V, '1' OV, ‘0’ 1k -OVin 36 PRELIMINARY PROCEDURE 1. Read the lab. 2. Number the pins on the gates of each circuit in the procedure. 3. Determine the Prelab X output (1 or 0) column corresponding to each figure in the procedure. PROCEDURE Build Figure 3.2 on a breadboard and use either a switch or a wire to implement the switch. Measure the voltage at node Vout when the switch is open and closed. 1. Switch State Open Close Table 3.2 A B Figure 3. 4 A 0 0 1 1 Table 3. 3 A 2. Build the following circuits and complete their corresponding table. Use a DMM to measure and record the output voltage for each input combination, as well as determine its binary representation. B Inputs Figure 3.5 B 0 1 0 1 Pull-Down, Voltage, Vin Inputs A 0 0 1 S.22 V B 0 1 0 a. Figure 3.4 through 3.13 and Table 3.3 through 3.12, respectively. D 7400 Prelab, X Binary Value, (1 or 0) 7402 Ö 1 Prelab, X Output X 1 Pull-Up, Voltage, Vin 5.02V 0.27mV Output X O Binary Value, (1 or 0) Measured Output Voltage 4.42V 4.34 V 4.84 v 132 V Measured Output Voltage 3.67 v 0.062 V 0.062 V 37 Table 3. 4 A Figure 3.6 Inputs A 1 0 Table 3.5 A Figure 3. 7 Inputs A 1 1 0 Table 3. 6 A Figure 3.8 Inputs A 1 0 1 7404 Prelab Output X D 7400 Prelab Output X ) 7402 Prelab Output X O Output X Output X 1 Output X Measured Output Voltage 0.108 V 4.42V Measured Output Voltage 0.001 V 5.02 V Measured Output Voltage 002 V 0.0654 3.42V 38 Table 3. 7 A ure 3.9 Inputs A 1 0 Table 3.8 B Figure 3. 10 Inputs A A 0 0 1 1 Table 3. 9 Figure 3. 11 B 0 1 0 1 Inputs A 0 0 1 1 B 0 1 0 1 Da 7402 Prelab Output X 7402 7402 Prelab, X 7400 Prelab, X a 7402 Output X 7402 1 1 DA 7400 X Output X Output X Measured Output Voltage 4.17 V 4.16 V Measured Output Voltage ५.2 v 4.2V 4.21 4.2 V Measured Output Voltage 39See Answer
Q2:PRACTICAL EXAM DEFINITION H O D G S 1 2 3 4 4 5 5 f a N L 6 7 8 678 b e g C dSee Answer
Q3: ECE2411 Logic Circuits II – Lab #1 Submission Details: For all problems, (1) submit your typed Verilog code (.v) and (2) report file (see exemplary report file on Canvas) with the waveforms (via screen capture). A Verilog hand-written solution with no simulation will receive no credit. O ABCD O Problem 1 [20 pts] (a) Write a Verilog code of the following combinational network using concurrent statements. Assume that all gate delays are zero. (b) Test your design with the following input combinations and provide waveforms. 1101 ABCD = 1011 2/9/24 ACD A O O O BADB A C Lab Assignment #1 A 0 0 0 1 1 Problem 2 [40 pts] (a) Write Verilog code for a 1-bit full subtractor using logic equations. The truth table for 1-bit full subtractor is shown below. B Bin 0 0 0 1 D 0 0 0 1 1 0 1 1 Diff Bout 0 1 1 0 0 Spring 2024 [Full score: 100 pts] D 1 (b) Test your design with the following input combinations and provide waveforms. A = 0, B = 0, Bin = 1 A = 0, B = 1, Bin = 0 A = 1, B = 0, Bin = 1 A = 1, B = 1, Bin = 0 -Z 1/2 ECE2411 Logic Circuits II - Lab #1 Spring 2024 (c) Write a Verilog code for a 5-bit full subtractor using your 1-bit full subtractor defined in (a). (d) Test your design with the following input combinations and provide waveforms. A = 10001, B = 00011, Bin 0 A = 11001, B = 00111, Bin = 1 O O Problem 3 [40 pts] (a) Write a Verilog code for a simple Arithmetic and Logic Unit (ALU) that implements 8 functions as described in Table 1. Table 1 shows the encoding of the control input. (** Read the design restrictions carefully) (b) Test your design (all for operations) by providing proper inputs and observe outputs on the waveform window. You need to come up with inputs and expected outputs. The 6-bit ALU has the following inputs and outputs: Inputs Control 000 001 010 011 100 101 110 111 2/9/24 = Outputs A: 5-bit input [a positive number; no sign bit] B: 5-bit input [a positive number; no sign bit] Cin: 1-bit input Control: 3-bit control input o Output: 5-bit output O Cout: 1-bit output EQ_check A >>3 A >>>3 Table 1: ALU Instructions Operation Output: A + B + Cin; Cout: a carry Output: A - B - Cin; Cout: a carry Output: A when Cin=0; B when Cin=1 Instruction Add Sub Mux -A (negative A) | Output: ~A + 1 Xor Output: A xor B Output: 0 when A==B; 1 otherwise Output: logical shift right by 3 Output: arithmetic shift right by 3 Design guideline use behavioral method use behavioral method use a case statement use 2's complement use a concatenation operator The following things should be taken care of: Use a case statement that checks the "Control" and acts on A, B, and Cin as described in Table 1. (** case statement should be in 'always' block) ● All the ALU operations are completely combinational. Verilog coding should follow the given design guidelines described in Table 1. 2/2See Answer
Q4:5. For the provided truth table, answer the following questions: ΧΥΖ | Output | 1 1 0 1 1 1 1 1 1 1 1 10 1 0 1 1 1 | 0 5.1 Write out the sum of products (SOP) for output as a function of X, Y, and Z. 0 0 0 001 0 1 0 0 1 1 1 0 0 10 1 5.2 Minimize the expression. 5.3 Implement the minimized function as a network of logic gates./nwill S.1 X 0 0 0 O 1 1 1 1 Y 0 0 1 1 O O 1 1 2 Output | 0 1 01 1 1 O Sop for out put 1 1 O 1 | 0 010 1 | 0 | 1 1 X'Y'2' + x'Y 2' + x²y2 + x Y'2'/n5.2 16 3 WY will minimize minimised Sop- Y 2 12 00 0 1 11 X- Y- 2' sop using 01 11 10 (1 1 y'2' + x'Y JY'₂! K-map- D x'y Y'2' + X'YSee Answer
Q5: Applied Electronics (UFMFHT-30-1) Finite State Machines Simulation Equipment Lab Objectives Upon completion of this lab, you should be able to design, implement, and simulate of a Moore-type Finite State Machine in both schematic and VHDL. 1. Quartus Prime Allocated Time: 2 hours OO TEXAS Panasonic TRUMENTS வசலசலக்கம் DO AMAKARA DEO-CV Cyclone terasIC AUTERA. ISSI AUSTIER 1 FPGA RESET யார் அற Figure 1: DE0-CV Development Board DANS OP 10 T Year 2023/2024 del Lab 8 Applied Electronics (UFMFHT-30-1) Introduction Synchronous sequential circuits are realised using combinational logic and one or more flip-flops. The general structure of such a circuit is shown in the figure 1 below. W Clock Combinational circuit Flip-flops Combinational circuit Year 2023/2024 ㅏ 2 Z Figure 1: FSM The circuit has a set of primary inputs, W, and produces a set of outputs, Z. The values of the outputs of the flip-flops are referred to as the state, Q, of the circuit. Under control of the clock signal, the flip-flop outputs change their state as determined by the combinational logic that feeds the inputs of these flip-flops. Thus, the circuit moves from one state to another. To ensure that only one transition from one state to another takes place during one clock cycle, the flip-flops must be of the edge-triggered type. They can be triggered either by the positive (0 to 1 transition) or by the negative (1 to 0 transition) edge of the clock. We will use the term active clock edge to refer to the clock edge that causes the change in state. The combinational logic that provides the input signals to the flip-flops derives its inputs from two sources: the primary inputs, W, and the present (current) outputs of the flip- flops, Q. Thus, changes in state depend on both the present state and the values of the primary inputs. Figure 1 indicates that the outputs of the sequential circuit are generated by another combinational circuit, such that the outputs are a function of the present state of the flip- flops and of the primary inputs. Although the outputs always depend on the present state, they do not necessarily have to depend directly on the primary inputs. Thus, the connection shown in pink in the figure may or may not exist. To distinguish between these two possibilities, it is customary to say that sequential circuits whose outputs depend only on the state of the circuit are of Moore type, while those whose outputs depend on both the state and the primary inputs are of Mealy type. These names are in honor of Edward Moore and George Mealy, who investigated the behavior of such circuits in the 1950s. Applied Electronics (UFMFHT-30-1) Sequential circuits are also called finite state machines (FSMs), which is a more formal name that is often found in technical literature. The name derives from the fact that the functional behaviour of these circuits can be represented using a finite number of states. Basic Design Steps We will introduce the techniques for designing sequential circuits by means of a simple example. Suppose that we wish to design a circuit that meets the following specification: Year 2023/2024 1. The circuit has one input, w, and one output, z. 2. All changes in the circuit occur on the positive edge of a clock signal. 3. The output z is equal to 1 if during two immediately preceding clock cycles the input w was equal to 1. Otherwise, the value of z is equal to 0. Thus, the circuit detects if two or more consecutive 1s occur on its input w. Circuits that detect the occurrence of a pattern on its input(s) are referred to as sequence detectors. From this specification it is apparent that the output z cannot depend solely on the present value of w. To illustrate this, consider the sequence of values of the w and z signals during 11 clock cycles, as shown in Figure 2. The values of w are assumed arbitrarily; the values of z correspond to our specification. These sequences of input and output values indicate that for a given input value the output may be either 0 or 1. For example, w = 0 during clock cycles t2 and t5, but z = 0 during t2 and z = 1 during t5. Similarly, w = 1 during t1 and t8, but z = 0 during t1 and z = 1 during t8. This means that z is not determined only by the present value of w, so there must exist different states in the circuit that determine the value of z. Clock cycle: to t₁ t3 t4 t5 t6 0 1 0 1 1 0 0 00 001 w: Z: Figure 2: Sequence of input and output signals tg tg t10 1 0 1 1 0 1 001 State Diagram The first step in designing a finite state machine is to determine how many states are needed and which transitions are possible from one state to another. There is no set procedure for this task. The designer must think carefully about what the machine must accomplish. A good way to begin is to select one particular state as a starting state; this is the state that the circuit should enter when power is first turned on or when a reset signal is applied. For our example let us assume that the starting state is called state A. As long as the input w is 0, the circuit need not do anything, and so each active clock edge should result in the circuit remaining in state A. When w becomes equal to 1, the machine should recognize this, and move to a different state, which we will call state B. This transition Applied Electronics (UFMFHT-30-1) Year 2023/2024 takes place on the next active clock edge after w has become equal to 1. In state B, as in state A, the circuit should keep the value of output z at 0, because it has not yet seen w = 1 for two consecutive clock cycles. When in state B, if w is 0 at the next active clock edge, the circuit should move back to state A. However, if w = 1 when in state B, the circuit should change to a third state, called C, and it should then generate an output z = 1. The circuit should remain in state C as long as w = 1 and should continue to maintain z = = 1. When w becomes 0, the machine should move back to state A. Since the preceding description handles all possible values of input w that the machine can encounter in its various states, we can conclude that three states are needed to implement the desired machine. Now that we have determined in an informal way the possible transitions between states, we will describe a more formal procedure that can be used to design the corresponding sequential circuit. Behavior of a sequential circuit can be described in several different ways. The conceptually simplest method is to use a pictorial representation in the form of a state diagram, which is a graph that depicts states of the circuit as nodes (circ ) and transitions between states as directed arcs. The state diagram in Figure 3 defines the behavior that corresponds to our specification. States A, B, and C appear as nodes in the diagram. Node A represents the starting state, and it is also the state that the circuit will reach after an input w = 0 is applied. In this state the output z should be 0, which is indicated as A/z=0 in the node. The circuit should remain in state A as long as w = 0, which is indicated by an arc with a label w = 0 that originates and terminates at this node. The first occurrence of w = = 1 (following the condition w = 0) is recorded by moving from state A to state B. This transition is indicated on the graph by an arc originating at A and terminating at B. The label w = 1 on this arc denotes the input value that causes the transition. In state B the output remains at 0, which is indicated as B/z=0 in the node. When the circuit is in state B, it will change to state C if w is still equal to 1 at the next active clock edge. In state C the output z becomes equal to 1. If w stays at 1 during subsequent clock cycles, the circuit will remain in state C maintaining z = 1. However, if w becomes 0 when the circuit is either in state B or in state C, the next active clock edge will cause a transition to state A to take place. 4 Applied Electronics (UFMFHT-30-1) w = 0 State Table Reset A/z = 0 w = 0 w = 1 Present state W = 0 A B C C/z = 1 W = 1 Figure 3: state Diagram of a simple sequential circuit In the diagram we indicated that the Reset input is used to force the circuit into state A, which is possible regardless of what state the circuit happens to be in. We could treat Reset as just another input to the circuit and show a transition from each state to the starting state A under control of the input Reset. This would complicate the diagram unnecessarily. States in a finite state machine are implemented using flip-flops. Since flip- flops usually have reset capability, we can assume that the Reset input is used to clear all flip-flops to 0 by using this capability. We will indicate this as shown in Figure 3 to keep the diagrams as simple as possible. w=0 A A A B/z = 0 w = 1 Although the state diagram provides a description of the behavior of a sequential circuit that is easy to understand, to proceed with the implementation of the circuit, it is convenient to translate the information contained in the state diagram into a tabular form. Figure 4 shows the state table for our sequential circuit. The table indicates all transitions from each present state to the next state for different values of the input signal. Note that the output z is specified with respect to the present state, namely, the state that the circuit is in at present time. Note also that we did not include the Reset input; instead, we made an implicit assumption that the first state in the table is the starting state. Next state w = 1 B C C Output Z Year 2023/2024 0 0 1 Figure 4: State table for the sequential circuit in Figure 3See Answer
Q6: Applied Electronics (UFMFHT-30-1) VHDL for Sequential Circuits Lab Objectives Upon completion of this lab, you should be able to 1. Use VHDL Sequential Statements to Implement D Flip Flops. 2. Use Different Approaches to Implement Synchronous Counters. Equipment 1. Quartus Prime 2. DE0-CV Development Board (Figure 1) 3. USB Cable Allocated Time: 2 hours OO MER TEXAS Panasonic 28.8.8.8.8.8. Lab 7 - VHDL for Sequential Circuits A DEO-CV Cyclone terasIC ADERA. ISSI gggg 12:0 10 29 30 OF 10 1 Figure 1: DE0-CV Development Board $::::::: Year 2023/2024 Lab 7 Page 1 Applied Electronics (UFMFHT-30-1) I. Background I.1 Sequential Statements: I.1.1 "Process" Statement A process is a set of sequential instructions executed in a predefined order. A process has a name, which is optional. A process has a sensitivity list. The execution of statements takes place in response to changes of the signals in the sensitivity list. The sequence of statements is sequentially evaluated. The syntax of the process statement is shown in figure 2. I.1.2. "if" Statement [name:] process (sensitivity_list) Declarations; I.1.3. "case" Statement sequence-of-statements; end process; Figure 2: The "Process" Statement In VHDL, "if" is a statement that is used to conditionally execute at least one sequential statement. The execution depends on a certain condition. It is possible to nest statements, controlled by different conditions using "elseif" branches (or "else if"). While the number of "elseif" is unlimited, there is only one "else" branch. The “else" branch is the last instruction and comes at the end before the "elseif" statement. What comes between the square brackets [ ] is optional. The syntax of the “if” statement is shown in figure 3. begin if (condition1) then Sequence_of_statements; [elsif (condition2) then Sequence_of_statements; elsif (condition3) then else Sequence_of_statements; endif; [Sequence_of_statements]; Lab 7 - VHDL for Sequential Circuits .] Year 2023/2024 Figure 3: The "if" Statement Depending on the value of an associated expression, the "case" statement selects for execution one of several alternative sequences of statements. The syntax of the case statement is shown in figure 4. Page 2 Applied Electronics (UFMFHT-30-1) case expression is when choice => sequential_statement; when choice => sequential_statement; when choice => sequential_statement; end case; Figure 4: The "Case" Statement I.2 Implementing Sequential Circuits Using VHDL I.2.1 Clocked D Flip Flops A D flip flop, as illustrated in figure 5, has two synchronous inputs D and Clk (clock) and two asynchronous inputs PRN (set) and CLRN (reset). The outputs of the flip flop are Q and Q (inverted output), respectively. The operation of a D flip flop is very simple and is illustrated in Table 1. When the asynchronous inputs are HIGH (PRN = 1 and CLRN = 1) and at the positive transition of the clock signal, the input is assigned to the output (Q = D). The flip flop is reset when PRN 1 and CLRN = = 0. The flip flop is set when PRN = 0 and CLRN = 1. D D 0 1 Lab 7 - VHDL for Sequential Circuits O PRN Clk Q CLRN Figure 5: D clocked Flip Flop Clk Q ↑ ↑ 1 Table 1: Truth Table of a D Flip Flop Year 2023/2024 The VHDL code that implements a simple D flip flop is shown in figure 6. Notice that the two asynchronous inputs PRN (Set) and CLRN (Clear) have been ignored in the VHDL description - as well as the inverted output -. Page 3 Applied Electronics (UFMFHT-30-1) library ieee; use ieee.std_logic_1164.all; entity Dflipflop is port ( clock, D in std_logic; : out std_logic); Q end entity; architecture ff of Dflipflop is begin process (clock) begin if (clock = '1' and clock'event) then Q <= D; end if; end process; end ff; Figure 6: VHDL Implementation of D Flip Flop The VHDL de ription of figure 6 could be easily expanded to include both asynchronous inputs and the inverted output, respectively. The code could be then used as a building block (component) in structural VHDL models to implement shift registers and counters. I.2.2. Synchronous Counters In both Lecture 6 and Lab 6, the methodology for designing synchronous counters using JK flip flops has been introduced. In synchronous counters, the flip flops are simultaneously clocked using the same clock signal. Figure 7 shows the state transition diagram of a MOD 5 synchronous counter as introduced in both lecture 6 and lab 6. 110 111 101 Lab 7 - VHDL for Sequential Circuits ............ Qo Q₁ Q₂ 000 100 001 011 010 Year 2023/2024 Figure 7: State Transition Diagram of the 3-bit MOD 5 Synchronous Counter The digital circuit that implements the MOD 5 counter is illustrated in figure 8. Page 4 Applied Electronics (UFMFHT-30-1) Clock Q₂ Q₁ J Clk '1' K Qo begin library ieee; use ieee.std_logic_1164.all; Qo entity Syncount5 is port (clock: in std_logic; Q end Syncount5; Qo+Q₂ Figure 8: 3-bit MOD 5 Synchronous Counter J Clk Q <= count; end count5; K architecture count5 of Syncount5 is end process; Q Lab 7 - VHDL for Sequential Circuits Q₁ Using sequential statements such process, case and if, different VHDL implementations could be envisaged. Two of such implementations are illustrated in figure 9 and figure 10, respectively. : out std_logic_vector (2 downto 0)); process (clock) variable count: std_logic_vector (2 downto 0); begin if (clock = '1' and clock'event) then case count is when "000" => count := "001"; => count := "010"; when "001" when "010" => count := "011"; when "011" => count := "100"; when "100" => count := "000"; when others => count :="000"; end case; end if; '1' Figure 9: VHDL Description of a MOD 5 Synchronous Counter using "process" and "case" Statements J Year 2023/2024 Clk K 2₂ Page 5See Answer
Q7:3 Complex Gates Normally, an XOR gate can be formed by using other functions such as from AND and OR gates. However, we can use a little trick to help us make the XOR and subsequently, the full adder more robust. If we look at the basic equations for an xor gate, it is: fzor = AⓇB With some simple applications of DeMorgan's Theorem, the xor gate can be broken into the following: fror (A-B)-(A-B) = (A+B)-(A + B) = A-B+A-B This can be easily be built in CMOS using the techniques we utilized during the first part of the semester. Figure 1: Sample Floorplan. A B XOR 0 0 0 0 1 1 1 0 1 1 1 0 Table 1: XOR Truth table.See Answer
Q8:2.1 Floorplanning Just like our layout assignments, without a careful plan on how you actually put together your circuits, can lead to hours of pain and agony. This is one of the great things about the stick diagram. One of the ways to extend this to higher level designs, especially designs that utilize hierarchy, is to use floorplanning. Floorplanning involves the simple diagramming of your circuit and how it gets put together. As we learned in lecture, a stick diagram may help us to visualize the structure, but it does not help us with the sizing. You can extend this by using pitch. Pitch is the distance, usually between two metals, between each layer. There are various ways to measure the pitch, such as between the center of a metal and its next edge. One way that you can incorporate this into your stick diagrams is to allow a 8 lambda pitch between each contact. Of course, you will have to account for the minimal width of each diffusion region, but it can help you with getting the dimensions of each cell. Once you have a more or less idea of the size of your cell, you can use this to floorplan your layout. When utilizing hierarchy, certain functions will use each other ostensibly. For example, an AND gate would utilize an NAND and and inverter gate. How you put them together, would involve high-level floorplanning. In other words, putting objects or blocks together and placing dimensions together to get an idea of the size necessary. There may be many times when you have to floorplan your circuit to fit a certain size. Therefore, the better the floorplan, the better the implementation. An example of a floorplan is shown in Figure 1.See Answer
Q9: VLSI Design Project ECEN 4303: Digital Integrated Circuit Design Fall 2023 Semester Version 1.0.0* 1 Introduction to Bit Slices This projects involves an intense project which you will design a 8-bit custom-based datapath slice. If you get done early, you could integrate some standard-cell parts to fully complete the block as well as other mathematical computations. Extra credit is available if you fabricate your design which is available to all who take this class. Datapath layout is often performed in custom-level cells for several reasons [1]. The datapath is usually the portion of a circuit that performs the majority of the useful work and contains the circuit's critical path. Therefore, it is worthwhile to make the datpath as fast as possible. Trained mask designers spend hours trying to produce dense and efficient layouts that can minimize the delays along a circuit's critical path or exhibit low power characteristics. The high density is also important to make the layout as compact as possible, since datapath layout is often repeated. Although the custom portion of this design is not super critical to the process, the overall idea of the project will give you a sense of what is needed to design integrated circuits as a whole. It also gives you an idea how custom-level design is critical to target a specific integrated circuit for speed and/or power. In this project you will putting together several parts within a custom block, such as an adder, multiplexor, and register. For this assignment, utilizing a bit slice technique will help you complete the design more efficiently. Bit-slicing is a popular technique in partitioning designs, so that they are more manageable [1]. This is fairly common in VLSI, since we would like to minimize the amount of time we spend doing custom level layout because it takes a majority of the time in most designs. A bit-slice involves designing datapath elements together for one bit and then repeating the cells in the direction of the word slice. Careful attention to floorplanning and recognizing certain repetitive areas in a cell can lead to good compact designs. 2 Planning Layout The use of hierarchy within a layout is critical. Many people fail to see the correlation between object- oriented design and hardware. However, these ideas behind the Object Oriented paradigm are extensively used within the hardware domain. Re-utilization of layout cells can greatly decrease your overall complexity, simplify debugging and limit your design time. Creating diagrams of you design in terms of its hierarchy is also recommended. For example, a full adder can be made with two xor gates and an or gate. Similarly, an exclusive-or (XOR) gate can be made with NAND, NOR, and Inverter gates. *Note that this document is updated periodically to provide you with the most reliable information to complete the project. Although previous versions of this document are basically correct, frequent revisions are made in order to help you save time and not to hinder your performance. Therefore, make sure you check back periodically for updates. I will add revision numbers to help you identify which version of this document you have. In this design, try to keep all the ndiff regions near the GND line and the pdiff regions near the VDD line. This is because of the need for body contacts. In general, inputs should be on the left and the top sides of the cells and the outputs should be on the right and the bottom. Make all the cells the same height so that the VDD and GND lines are continuous when abutment is used. This process of keeping everything a certain height is called pitch-matching. 2.1 Floorplanning Just like our layout assignments, without a careful plan on how you actually put together your circuits, can lead to hours of pain and agony. This is one of the great things about the stick diagram. One of the ways to extend this to higher level designs, especially designs that utilize hierarchy, is to use floorplanning. Floorplanning involves the simple diagramming of your circuit and how it gets put together. As we learned in lecture, a stick diagram may help us to visualize the structure, but it does not help us with the sizing. You can extend this by using pitch. Pitch is the distance, usually between two metals, between each layer. There are various ways to measure the pitch, such as between the center of a metal and its next edge. One way that you can incorporate this into your stick diagrams is to allow a 8 lambda pitch between each contact. Of course, you will have to account for the minimal width of each diffusion region, but it can help you with getting the dimensions of each cell. Once you have a more or less idea of the size of your cell, you can use this to floorplan your layout. When utilizing hierarchy, certain functions will use each other ostensibly. For example, an AND gate would utilize an NAND and and inverter gate. How you put them together, would involve high-level floorplanning. In other words, putting objects or blocks together and placing dimensions together to get an idea of the size necessary. There may be many times when you have to floorplan your circuit to fit a certain size. Therefore, the better the floorplan, the better the implementation. An example of a floorplan is shown in Figure 1. 3 Complex Gates Normally, an XOR gate can be formed by using other functions such as from AND and OR gates. However, we can use a little trick to help us make the XOR and subsequently, the full adder more robust. If we look at the basic equations for an xor gate, it is: y lambda fxor w lambda With some simple applications of DeMorgan's Theorem, the xor gate can be broken into the following: fxor (A · B) · (A · B) (A + B) · (A + B) A. B+ A.B This can be easily be built in CMOS using the techniques we utilized during the first part of the semester. = = = = x lambda XOR A B NAND z lambda. 111 ||||| | Vdd 2 Gnd Vdd Function 1 Function 2 Figure 1: Sample Floorplan. 3.1 Mirror Circuits The XOR circuit is one of the most beneficial circuits to design engineers. Not only is it vital to adder circuits, but it plays a key role in cryptographic circuits, such as parity generation. Therefore, anything that can be done to speed up this circuits is monumental. One method of making the XOR circuit more compact and quicker is to use the mirror circuit. The mirror circuit is basically where the NMOS and the PMOS gates have exactly the same structure. However, they do not use series-parallel, but use many of the same characteristics (i.e. the mirror does not have any parallel structures except at the folding point). 3.2 Full Adder The full adder is the basi cell for most dd full adder cell are The origin of the mirror circuit comes from the truth table of the circuit to be designed. For the XOR gate, it is easy to see that it appears the truth table is flipped as shown in Table 1. a D In order to construct the mirror XOR gate, it is necessary to remove the parallel structure for the PUN group of A B. This is achieved by removing the parallel structure normally found in the XOR gate (i.e. (Ā · B) + (A · B)) and rewriting the equation. The circuit is shown in Figure 2. It is important to note that although the basic element of an XOR gate is built-using mirror circuits, that it still requires inverters. This is a fundamental problem with most circuit styles today and it appeals strongly to static CMOS design. Other circuit styles such as dynamic CMOS can not easily make an inverted signal, since dynamic CMOS is non-inverting. Therefore, although dynamic circuits tend to be much faster than static CMOS circuits, they still need inverters. Most dynamic logic styles in CMOS still utilize the static CMOS inverter due to is ability to create easy inversions and PMOS' ability to be the "perfect" load. vdd A 0 0 1 1 Table 1: XOR Truth table. 1.68 0.15 0.84 0.15 B 0 1 0 1 gnd Sum Cout = = Because the full adder is basically counting whether or not one value is above a certain level, the full adder is typically called a (3, 2) counter. This is because there are 3 inputs and 2 outputs. Similar to the XOR gate, the full adder can utilize a mirror structure as seen by the full adder's truth table. Although Cin does not appear to have any mirrored structure, it is clearly evident that Sum does. implementations. The basic equations for addition using the A B Cin A. B+ Cin (A + B) ad[ XOR 0 1 1 0 1.68 0.15 1.68 0.15 0.84 0.15 0.84 0.15 vdd gnd 3 1.68 0.15 1.68 0.15 0.84 0.15 0.84 0.15 ]p-ab -D out a b vdd 1.68 0.15 0.84 0.15 gnd Figure 2: XOR Function Using Mirror Circuits. b CD d[ 0.42 0.15 0.42 0.15 vdd b D ဤ 0.42 0.15 0.42 0.15 b gnd 0.42 0.15 0.42 0.15 a D b D b D a D vdd 0.42 0.15 0.42 0.15 0.42 0.15 0.42 0.15 gnd a d 0.42 0.15 0.42 0.15 b D b D vdd 0.42 0.15 0.42 0.15 0.42 0.15 0.42 0.15 gnd 4 CD c 0.42 0.15 0.42 0.15 a c bood[ cod[ b vdd ad[ Figure 3: (3,2) Counter Function Using Mirror Circuits. 0.42 0.15 0.42 0.15 0.42 0.15 0.42 0.15 0.42 0.15 0.42 0.15 gnd sum -D cout The circuit is shown in Figure 3. Again, careful use of an inverter is needed as shown in the diagram. The Full Adder is made from the 28 transistor Full Adder cell. You may also add specific logic to perform either a logic addition or subtraction. This is easily accomplished in most processors by utilizing an exclusive-or (xor) on the second input operand. Normally, a bit signal can be used to to indicate either two's complement addition or subtraction. Subtraction is the same as addition except we add the negative version of a given operand. That is, instead of adding b + a, the operation is able to subtract a from b by complementing a (i.e. b+ (−a)) via a subtract signal. Since this project will utilize two's complement addition/subtraction, your project must be able to add the magic one or unit in the last position (ulp), because it is a radix-complement of the binary system. Therefore, the adder will calculate b + −a +ulp [2]. An ulp is an acronym that signifies the unit in the last place [3]. This terminology is the correct method of describing adding one to the number, since we do not know if the number is an integer or a fraction. For the remainder of this project definition, the phrase ulp will be utilized. This year we will give you the mirror adder circuit, but you will need to LVS it to make sure it works. It is also adviable to utilize this cell to help craft the register design. Since the register cell will probably be larger, it is advisable to be careful on how you design this circuit. 3.3 Registers Building registers in one of most crucial elements that exists in any datapath design. This is because they are crucial to storing data and re-using it for future use. Therefore, having efficient, low-latency, minimal area design is important for any design. In this section, you will implement a register that will follow your adder. The fundamental building block of a d flip flop is the d or transparent latch. And there are many approaches for constructing latches. One very common technique involves the use of transmission gate mul- tiplexers. Multiplexer-based latches can provide similar functionality to the SR latch, but has the important added advantage that the sizing of devices only affects performance and is not critical to the functionality. Some systems use Static Random Access Memory (SRAM) to build registers, however, we are going to simplify things. To make things easier, you will be implementing a complete D flip-flop, similar to the Full Adder design. A better and easier design that you can use for this project is shown in Figure 4. Although hierarchical designs can sometimes be better for more structured gates, some gates, such as the D-flip-flop, are better when they are structured as an individual gate. Ultimately, circuit-level simulation is best suited to adequately determine the objective in which to optimize a gate. Figure 4 shows the schematic representation DD 1.68 0.84 0.15 CIK B 0.42 0.15 0.42 and 0.42 0.15 0.15 E I I FEET 0.15 042 015 AA diffpos.cit Scale: 0.233645 (5935X) n 0000 I □ 1 GR h 0.15 0.15 0.42 0.15 Figure 4: Transistor Level Schematic of a Positive D flip-flop Using Transmission Gates. 5 0.42 0.15 and 0.42 0.15 0 0.42 0.42 0.15 TR 0.42 0.15 Figure 5: Sample Transistor Gate Implementation of a Positive D flip-flop Using Transmission Gates. and Figure 5 shows a sample layout previously done by the author of this project (to help you with the floorplanning). Sequencing elements, such as a d flip flop, also often accept an enable input. When enable is low, the element retains its state independently of the clock. The enable can be performed with an input multiplexer or clock gating, as shown in Figure 6. The input multiplexer feeds back the old state when the element is disabled. The multiplexer adds area and delay. Clock gating does not affect delay from the data input and the AND gate can be shared among multiple clocked elements. Moreover, it significantly reduces power consumption because the clock on the disabled element does not toggle. However, the AND gate delays the clock, potentially introducing clock skew. You can also addresses techniques to minimize the skew by building the AND gate into the final buffer of the clock distribution network. however, the enable must be stable while the clock is high to prevent glitches on the clock. 3.4 Bitslicing This project's task is simple and two-folded. The main task is for you to understand the importance of bit-slicing and the second is to work on integrating many of the ideas you had throughout the semester into one package or learning experience. The bad part about this is that it will involve you to task your time throughout the semester or you will not have enough time to complete this project. Therefore, please pay attention to time milestones when working on this project. The bitslicing project will involve a portion of a design based on simple computation. This part could be utilized to implement a chip that can compute any function, similar to what is found on a typical datapath/nNeed to submit 1-bit FA xschem & LVS 1-bit DFF xschem stick diagrams of leaf cells create leaf cells and perform LVS assembled top-level Magic and perform LVS ngspice testing reportSee Answer
Q10:Question 6 (20 points): Optimize the circuit in Figure to obtain the least delay along the path from A to B when the electrical effort of the path is 4.5. C D D 4.5C 450 4.5CSee Answer
Q11:Question 5 (40 points): Consider the following Circuit. Assume timings for both D flip-flops are identical, and they are: t=0 f New Data Input Clock D DFF-1 DFF ►C Q1 Combinational Logic Td =Time delay Wire Delay D2 DFF-2 DFF DC Q*b D-Flip-flop Setup time = T₁= 15 psec • D-Flip-flop Hold time = T₁ = 20 psec • D-Flip-flop Clock-to-Q delay = To = 83 psec • Combinational Logic Delay = T₁ = 35 psec a) Compute the new data input uncertainty time interval (aperture time T₁). b) How long does it take for D-Flip-flip to process each new data? Out c) What is the earliest time that the rising edge of clock can be asserted for the new input data to be processed by DFF- 1?/nd) What is the earliest time that the output data of the first flip-flop, DFF-1, is valid at the input of the combinational logic? e) If there is no wire delay, what is the minimum clock period? f) What is the maximum acceptable wire delay (Clock Skew)?See Answer
Q12:Question 3 (20 points): Considering a circuit implementing F = A'BD + AC'D + BC'D, with probabilities of each input as p(A) = 0.3, p(B) = 0.4, p(C) = 0.5, and p(D) = 0.6. Assume all inputs are uncorrelated, and the circuit is fed by Vdd of 2V, running at 1GHz clock, and driving load of 200fF, calculate the switching power consumption.See Answer
Q13:A1 In a Verilog-HDL source description, what kind of statement uses the following format? and A1 (F, A, B, C); (2.5 marks) A2 Draw the correct logic symbol corresponding to the following Verilog-HDL module. module A2 (input A, B, output F); assign F = A | B; endmodule A3 Create the correct Continuous Assignment statement for the circuit shown in figure A3. Figure A3 AB T C D D A4 Given that the states of the flip-flops in Figure A4 are <Q2, Q1, Q0> = <0, 0, 0> initially, find out the correct sequence of decimal states from the alternatives given. CLK QO D CLK Q Figure A4 M Q1 (2.5 marks) D CLK (2.5 marks) Q2 (2.5 marks)See Answer
Q14:Design a CMOS logic gate that implements the logic function Y = ABC+DE based on the CMOS reference inverter. Select the transistor sizes to give the same delay as that of the reference inverter if the load capacitance is the same as that of the reference inverter.See Answer
Q15:(a) What is the logic function implemented by the gate in Fig. P7.84? (b) Design the PMOS transistor network. Select the device sizes for both the NMOS and PMOS transistors to give a delay of approximately one-half the delay of the CMOS reference inverter. C is the same. (c) What is the equivalent W/L ratio of the NMOS switching network when all of the NMOS transistors are on? (d) Repeat for the PMOS network.See Answer
Q16:This is CMOS 4-input NOR Gate, The will use LTSPICE software and IRSIM software to draw, run, and analyze... compare and contrast the resultsSee Answer
Q17:4. Create a truth table for below circuit. The inputs are R, L, and C and the outputs are X and Y.See Answer
Q18:2. Construct a complete truth table and timing diagram for a positive-edge-triggered D flip flop including present and clear inputs.See Answer
Q19:1. Discuss the difference between the combinational and sequential circuit.See Answer
Q20:• To introduce the NOR, NAND, XNOR gates • To study logic functions • To implement logic functions on the trainer board • To simulate logic functions using Logisim • To understand and find the truth table of Boolean expressionsSee Answer

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