# logic circuits vlsi homework help

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• Q1: Reconsider the three bit synchronous counter register described in the lecture notes. Use the counter symbol to control the lights of a street intersection. Street 1 has lights G1, Y1, R1 and street 2 has lightsG2, Y2, R2. ) Draw a schematic using the counter to make a counter that counts 000 to 101 and overflow back to count 000. There is a clock input and negative logic clear signal clrn. The reset state is 000. b) The following table shows that each light is green for two units of time, yellow for one unit of time, and red for three units of time. The u symbol indicates unused states. See Answer
• Q2: 8. Consider a three-bit register with the ability to parallel load a value or decrement by one. To implement the decrement capability use three half subtractors HSUB. The half subtractor truth table with inputs ai(bit in), bi (borrow in) and outputs bo (borrow out), do (bit out) is as follows. Three half subtractors are used to make a decrementer with positive logic enable input ena. The following function table summarizes the behavior of the register. See Answer
• Q3: 7. With regard to the the three bit synchronous counter register described in the lecture notes, describe the significance that the load signal has priority over the run signal. When its necessary to stop counting what is necessary for the counter to stop at its final value?See Answer
• Q4: 8. Use the Boolean functions developed in problem #4 to create a circuit in verilog HDL with four inputs(a,b,c,d) and four outputs (w,x,y,z) with each output equal to the result of problem #4. Show your HDL code as well as the simulation results.See Answer
• Q5: Assuming 4-bit signed binary numbers, calculate the result: 1111 + 0100 (your answer should be a 4-bit binary number: example: 0000)See Answer
• Q6: What is the minimum number gates needed to replicate the behavior of the function below using ONLY 2-input NAND gates: (ASSUME DOUBLE-RAIL Inputs: that is Q, Q', S, S', T,T,R,and R' are all available) - Your answer should be a number F = QRT+S'T+R'See Answer
• Q7: 8. Use the Boolean functions developed in problem #4 to create a circuit in verilog HDL with four inputs(a,b,c,d) and four outputs (w,x,y,z) with each output equal to the result of problem #4. Show your HDL code as well as the simulation results.See Answer
• Q8: Find the Hexamdecimal equivalent for the following 8-bit unsigned binary numbers See Answer
• Q9: Find the Decimal Equivalent for the following 8-bit signed binary number: 11011010 (use "-" for negative numbers, example: -11 )See Answer
• Q10: 7. Use the Boolean functions developed in problem #3 to create a circuit in verilog HDL with four inputs(a,b,c,d) and four outputs (w,x,y,z) with each output equal to the result of problem #3. Show your HDL code as well as the simulation results.See Answer
• Q11: Find the Decimal Equivalent for the following 8-bit unsigned binary number: 11011010 (use "-" for negative numbers, example: -11 )See Answer
• Q12: Find the decimal equivalent for (1011 0110) in 7,3,1,-2 weighted code (enter the result as one number ex: 99)See Answer
• Q13: Given 4-bit Signed Binary Numbers, which of the following operation will result in overflow (check all that apply) 1000 + 1111 1111 + 1111 0111 - 1111 0100 + 0100See Answer
• Q14: Use the Boolean functions developed in Problem 1 to create a circuit in verilog HDL with four inputs(a,b,c,d) and two outputs (F1, F2) with each output equal to the result of Problem 1. Show your HDL code as well as the simulation results.See Answer
• Q15: Find the current through each branch of the circuit in Figure 1. See Answer
• Q16: 2)Figure 2 shows a simple curent-divider circuit with two resistors in parallel and a voltage source. Show that the current through resistor R2, k is given by: I_{2}=\frac{R_{1}}{R_{1}+R_{2}} \times I s where Is is the total curent supplied by the souce. Figure 2.Current-Divider circuit.See Answer
• Q17: Use the PLA figure given at the end of the assignment to implement the given logic functions. Write what each product term P1 through P5 is assigned and draw in fuse diodes to show how each productt erm as well as resulting function is implemented. F1 3D A:B':С+ B:С'+ А-B':С ||See Answer
• Q18: Consider the following truth table: a) Draw a circuit for the logic function F as a sum of minterms using a3 to 8 decoder symbol with negative logic outputs as well as aNAND gates. b) In the same circuit as part a) use an AND gate to implement logic function G as a product of maxterms. c) Draw a circuit for the logic function G using a 4 by 1 multiplexer.The multiplexer has select inputs a1,a0. See Answer
• Q19: Find the Decimal Equivalent for the following 8-bit signed binary number: 01011010 (use "-" for negative numbers, example: -11 )See Answer
• Q20: Figure 2 outlines an Input / Output (I/O) port used for boundary scan testing of integrated circuits. Provide a research-based report (minimum 2000 words) that considers the following points as a minimum: (25 marks) Provide an introduction to boundary scan in your report, consider: what is boundaryscan, how it functions, where boundary scans are used, why they are important, andthe purpose of the various inputs to the boundary scan cell. Provide references whereappropriate. With reference to TDI and TDO explain how these ports may be arranged around apiece core logic to allow boundary scan testing Explain how the I/O ports may be configured as an input port with input datascanned into the cell for testing the core logic of an integrated circuit. Explain how the I/O port may be configured as an output port for capturing datafrom the core logic of an integrated circuit. Explain how these ports may be arranged for testing printed circuit board interconnections between pins of an integrated circuit.6.See Answer

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