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Q1: Reconsider the three bit synchronous counter register described in the lecture notes. Use the counter symbol to control the lights of a street intersection. Street 1 has lights G1, Y1, R1 and street 2 has lightsG2, Y2, R2. ) Draw a schematic using the counter to make a counter that counts 000 to 101 and overflow back to count 000. There is a clock input and negative logic clear signal clrn. The reset state is 000. b) The following table shows that each light is green for two units of time, yellow for one unit of time, and red for three units of time. The u symbol indicates unused states. See Answer
Q2: 8. Consider a three-bit register with the ability to parallel load a value or decrement by one. To implement the decrement capability use three half subtractors HSUB. The half subtractor truth table with inputs ai(bit in), bi (borrow in) and outputs bo (borrow out), do (bit out) is as follows. Three half subtractors are used to make a decrementer with positive logic enable input ena. The following function table summarizes the behavior of the register. See Answer
Q3: 8. Use the Boolean functions developed in problem #4 to create a circuit in verilog HDL with four inputs(a,b,c,d) and four outputs (w,x,y,z) with each output equal to the result of problem #4. Show your HDL code as well as the simulation results.See Answer
Q4: 8. Use the Boolean functions developed in problem #4 to create a circuit in verilog HDL with four inputs(a,b,c,d) and four outputs (w,x,y,z) with each output equal to the result of problem #4. Show your HDL code as well as the simulation results.See Answer
Q5: Given 4-bit Signed Binary Numbers, which of the following operation will result in overflow (check all that apply) 1000 + 1111 1111 + 1111 0111 - 1111 0100 + 0100See Answer
Q6: 2)Figure 2 shows a simple curent-divider circuit with two resistors in parallel and a voltage source. Show that the current through resistor R2, k is given by: I_{2}=\frac{R_{1}}{R_{1}+R_{2}} \times I s where Is is the total curent supplied by the souce. Figure 2.Current-Divider circuit.See Answer
Q7: Use the PLA figure given at the end of the assignment to implement the given logic functions. Write what each product term P1 through P5 is assigned and draw in fuse diodes to show how each productt erm as well as resulting function is implemented. F1 3D A:B':С+ B:С'+ А-B':С ||See Answer
Q8: Consider the following truth table: a) Draw a circuit for the logic function F as a sum of minterms using a3 to 8 decoder symbol with negative logic outputs as well as aNAND gates. b) In the same circuit as part a) use an AND gate to implement logic function G as a product of maxterms. c) Draw a circuit for the logic function G using a 4 by 1 multiplexer.The multiplexer has select inputs a1,a0. See Answer
Q9: Find the Decimal Equivalent for the following 8-bit signed binary number: 01011010 (use "-" for negative numbers, example: -11 )See Answer
Q10: Figure 2 outlines an Input / Output (I/O) port used for boundary scan testing of integrated circuits. Provide a research-based report (minimum 2000 words) that considers the following points as a minimum: (25 marks) Provide an introduction to boundary scan in your report, consider: what is boundaryscan, how it functions, where boundary scans are used, why they are important, andthe purpose of the various inputs to the boundary scan cell. Provide references whereappropriate. With reference to TDI and TDO explain how these ports may be arranged around apiece core logic to allow boundary scan testing Explain how the I/O ports may be configured as an input port with input datascanned into the cell for testing the core logic of an integrated circuit. Explain how the I/O port may be configured as an output port for capturing datafrom the core logic of an integrated circuit. Explain how these ports may be arranged for testing printed circuit board interconnections between pins of an integrated circuit.6.See Answer
Q11: ) The circuit shown in figure 1 is a 4-bit weighted resistor Digital to Analogue Converter (DAC). (a) Given that the logic inputs eo- e3 have a value of 0V for logic '0' and +5V for logic '1' and that a full-scale range (FSR) output of -15V is required from the DAC determine values for the resistors Ro. R3.(7 marks) (b) If the actual values of the resistors R0 - R3 were: R0=40k2, R1=16k2, R2=7.28k2,R3=5.72k. Determine the error voltage contributed to the output of the converter due to difference in the theoretical and actual values of the resistor when a logic '1' is applied to that resistor and only that resistor. Hence compile a set of error values in terms of LSB's for each of the bits 0-3.(7marks) (c) Given that your DAC circuit has output errors associated with each bit as shown in Table 1and is still operating with the values given in part (a): (i)Draw a graph (on the graph paper provided) of the output voltage of the DAC as a function of applied digital input value.(5 marks) (ii)Determine if the DAC is monotonic. (iii) Determine the linearity of the DAC. (iv) Determine the differential non-linearity of the DAC.See Answer
Q12: 7. Use the Boolean functions developed in problem #3 to create a circuit in verilog HDL with four inputs(a,b,c,d) and four outputs (w,x,y,z) with each output equal to the result of problem #3. Show your HDL code as well as the simulation results.See Answer
Q13: Suppose that when experimenting with Lab 4 we getDisplayA: 56 and DisplayB: 87. Which instance is driving thevalue 8 seen on the displays? See Answer
Q14:A1 In a Verilog-HDL source description, what kind of statement uses the following format? and A1 (F, A, B, C); (2.5 marks) A2 Draw the correct logic symbol corresponding to the following Verilog-HDL module. module A2 (input A, B, output F); assign F = A | B; endmodule A3 Create the correct Continuous Assignment statement for the circuit shown in figure A3. Figure A3 AB T C D D A4 Given that the states of the flip-flops in Figure A4 are <Q2, Q1, Q0> = <0, 0, 0> initially, find out the correct sequence of decimal states from the alternatives given. CLK QO D CLK Q Figure A4 M Q1 (2.5 marks) D CLK (2.5 marks) Q2 (2.5 marks)See Answer
Q15:A14 Write down the correct equivalent Verilog continuous assignment for Figure A14. B(1) ► A[1]► B[0) ► A[0] Jan 2023 1 Figure A14 KD5065: C Programming and Digital Systems A15 Figure A15 shows the K-Map of a sum-of-products logic circuit showing the groupings used to form the products. AB /B 00 01 11 10 01000 IC 1 10 C 1 B JA A Figure A15 M /B (2.5 marks) Given that the circuit contains timing hazards, what type of hazard is the circuit experiencing? (2.5 marks) A16 Referring to figure A15, what is the correct pair of input combinations, which if applied to the logic circuit inputs in sequence, would reveal the timing hazard. (2.5 marks)See Answer
Q16:Question 1 (30 points): Consider a basic 6-T SRAM cell assuming PMOS transistors with W = 4A, L = 3A, and NMOS transistors with L = 2A. Assume that un/up = 2, V₁N-0.3V, V₁= -0.4V, VDD = 1.2V. Find the smallest W for the NMOS transistors in the following conditions: BL WL AXL PUL V1 PDL VDD GND PUR PDR WL AXR BLB a) (15 pts) During writing and reading, V1 needs to be no greater than VTN- b) (15 pts) Repeat part (a), however this time assume that V1 needs to be no greater than VDD/3. For each part the sizes should be multiples of X, therefore fractional numbers should be rounded up.See Answer
Q17:Question 3 (20 points): Considering a circuit implementing F = A'BD + AC'D + BC'D, with probabilities of each input as p(A) = 0.3, p(B) = 0.4, p(C) = 0.5, and p(D) = 0.6. Assume all inputs are uncorrelated, and the circuit is fed by Vdd of 2V, running at 1GHz clock, and driving load of 200fF, calculate the switching power consumption.See Answer
Q18:Question 4 (40 points): Consider a 4-input static logic gate implementing Boolean function, z = A(B+C)+BCD. The input signal probabilities are given as: p(A) =p(D) = 0.25; p(B) = 0.33; p(C) = 0.5. a) (20 pts) Assuming that the inputs are uncorrelated and that all signals are temporally independent, what is the average power dissipation at the output of this gate if it is driving a 100 ff total load at 500 MHz and VDD = 1.2V? b) (20 pts) Next, assuming kn=kp=200uA/V2, Vtn= |Vtp|=0.3V, Tin=100ps and Tout=250ps, calculate short circuit power dissipation.See Answer
Q19:Question 5 (40 points): Consider the following Circuit. Assume timings for both D flip-flops are identical, and they are: t=0 f New Data Input Clock D DFF-1 DFF ►C Q1 Combinational Logic Td =Time delay Wire Delay D2 DFF-2 DFF DC Q*b D-Flip-flop Setup time = T₁= 15 psec • D-Flip-flop Hold time = T₁ = 20 psec • D-Flip-flop Clock-to-Q delay = To = 83 psec • Combinational Logic Delay = T₁ = 35 psec a) Compute the new data input uncertainty time interval (aperture time T₁). b) How long does it take for D-Flip-flip to process each new data? Out c) What is the earliest time that the rising edge of clock can be asserted for the new input data to be processed by DFF- 1?/nd) What is the earliest time that the output data of the first flip-flop, DFF-1, is valid at the input of the combinational logic? e) If there is no wire delay, what is the minimum clock period? f) What is the maximum acceptable wire delay (Clock Skew)?See Answer
Q20:Question 6 (20 points): Optimize the circuit in Figure to obtain the least delay along the path from A to B when the electrical effort of the path is 4.5. C D D 4.5C 450 4.5CSee Answer

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