3. Consider scaling a CMOS technology by S > 1. In order to maintain compatibility with existing system components, you decide to use constant voltage scaling.

In traditional constant voltage scaling, transistor widths scale inversely with S, Wα1/S. To avoid the power increases associated with constant voltage scaling, however, you decide to change the scaling factor for W. What should this new scaling factor be to maintain approximately constant power. Assume long-channel devices (i.e., neglect velocity saturation).

How does delay scale under this new methodology?

Assuming short-channel devices (i.e., velocity saturation), how would transistor widths have to scale to maintain the constant power requirement?