a) The structure of a synchronous digital circuit is shown in figure 1.1. It comprises five registers (Reg) and two combinational logic blocks (CL). The following timing data applies. CL1

InX or InY to V delay 1.4 ns CL1 InX or InY to C delay 1.5 ns CL2 either input to Vo delay 400 ps Register hold time 260 ps Register setup time 250 ps Register Propagation delay 320 ps State the number of flip-flops in the circuit, identify the critical path and calculate the maximum clock frequency. Explain your answers and show any working. b) Given the following data for a D-type flip-flop state which of the timing requirements for the flip-flop are violated, and when, in the timing diagram shown figure 1.2. Positive edge triggered clock Hold time 500 ps Setup time 500 ps Minimum clock pulse width 900 ps Propagation delay 880 ps c) For the circuit in figure 1.3 draw a timing diagram to show the wave forms on E, F,G, H and J in response to the inputs (A,B,C) shown in figure 1.3. Clearly indicate unknown values and make sure that your time axis is clear. Use the following information. All signals except C are 8-bit unsigned and shown as hexadecimal values. C is a single bit. R1, R2 and R3 are positive edge clocked registers. All registers are synchronously clocked by the signal "Clock" shown in figure 1.4,but not drawn on figure 1.3. The multiplexer (Mux) routes lo when sel=0 and Ii when sel=1. The adder's carry-in is at logic 0 and its carry-out is not connected. All components (registers, adder, mux) have a propagation delay of 2.5 ns. All registers start holding unknown values and do not have a reset.