Assignment 1 [40 points]: Design a 4-bit Ripple Carry Adder that adds two 4-bit inputs and produces a 4-bit Sum and 1-bit Carry Out outputs. a) Use VHDL for behavioral coding

(code for zero delay - no input to output delays). [5] b) Write a testbench with the following inputs to test out (a) above: 1010+ 0101 1100 + 0111 0101 + 0101 Demo results on Vivado. [5] c) Use VHDL for structural coding with basic gates to design Half-Adder and Full Adder structurally, and then use these intermediate components to structurally build up to the 4-bit Adder. All basic gates will have 1ns internal delays. [20] d) Using the testbench of (b), test out (c) above. Demo results on Vivado. [10]