Figure B3a shows a data exchange system that uses a single-bit shared bus line(SB) to pass digital information from a set of data transmitters, 'AQA3 and CO..C3',to data receivers 'B0..B3

and DO.D3'. All signals are 1-bit, apart from SA, SB, SCand SD, which are 2-bit (indicated by the 'x' enclosed within the terminal symbols). The two multiplexers (MUXS) at top-left and bottom-right of Fig. B3a use 2-bit select inputs 'SA' and 'SC' to choose a transmit channel (03). Similarly, the two de-multiplexers (DMXS) at top-right and bottom-left of Fig. B3a use 2-bit select inputs"SB' and 'SD' to choose a receive channel (03). Choose either the MUX or DMX and sketch a gate-level logic circuit implementation of the symbol (MUX or DMX). Depending upon which choice you made above, write down the Verilog-HDL description of the other symbol, Le if you sketched the logic circuit for the MUX (DMX), write down the Verilog description of the DMX (MUX). In your descriptions, you may make use of continuous assignment statements and/or primitive gate instantiations.(6 morke) Write down the name of the Verilog-HDL built-in primitive element that could be used to model the four three-state buffers connected to the shared bus 'SB', in Fig. B3a. Write down the values, in Verilog format, of the following control signals: SA, SB, SC, SD, ENA and ENB In order to perform the following data transfer operations in Fig. B3a: i.Transmit data from A3 to B1. Figure B3b shows a particular type of counter based on a shift register. The asynchronous set (S) and reset (R) inputs of the flip-flops are active-high, assume any unconnected inputs are at logic-0. (2 marks)Sketch a set of digital waveforms for the outputs, , of the counteralong with the clock input 'CIK. Assume the circuit has previously been reset bypulsing the Rst input to logic-1. (6 marks)Given that the frequency of the clock input 'Çlk' is 10 MHz, deduce the frequency of any Q output.