Lab Project: Structural Design of Sequential Circuits Problem Statement Design a circuit that increments a digit (0 - F) shown on the seven-segment display device once each second. The circuit has four pushbutton inputs: one button starts the counter, a second button stops the counter, a third button increments the counter, and the fourth button asynchronously resets all memory devices in the design. The system has the block diagram shown Fig. 1 below. You must create the 4-bit counter, a clock divider, a seven-segment display decoder, and a controller circuit. You may use any design tools or methods you wish. You must also create and submit a state diagram for the controller, together with K-maps showing the next-state and output circuits in your final report. Controller 4-bit counter 7-seg decoder BTN1 Start Run Cen B0 A BTN2 Stop B BTN3 Inc C B1 Clk divider B2 D Clk pin Clk Clk B3 E RST F RST G BTN4 Figure 1. Clock divider with a counter and a comparator Clock Divider A clock signal is needed in order for sequential circuits to function. Usually, the clock signal comes from a crystal oscillator on-board. The oscillator used on Intel FPGA boards usually ranges from 50MHz. However, some peripheral controllers do not need such a high frequency to operate. We can use a counter with a comparator to condition a flip-flop with an inverter to implement a clock divider that can control the output frequency of the on-board clock, slowing it to 1Hz. The block diagram of such a clock divider is shown in Fig. 2. Counter Comparator Q A ->clk EQ rst Constant En D Q clk > Clk clk div Rst rst Figure 2. Clock divider with a counter and a comparator. In the block diagram, the counter increases by 1 whenever the rising edge of clk arrives. It also resets its output to '0' when it reaches the constant number defined in the constant block. The comparator compares the output of the counter with the pre-defined constant and asserts EQ if the output of counter is equal to the pre-defined constant. When EQ is asserted, the output of the clock divider flips. Let's assume that the pre-defined number is 3, and the output of clock divider (clk_div) is initialized to 0. It takes three clock cycles before the output of the counter equals the pre-defined constant, 3. 2 pages Lab Project #10: Structural design of Sequential Circuits When it reaches 3, the output of clock divider (clk_div) turns to 1, and the counter resets itself. It takes another three cycles before the output of the counter equals the pre-defined constant, 3. When it reaches 3 again, clk_div turns back to 0. So, it takes 6 clock cycles before clk_div goes to 1 and returns to 0 again. As a result, the frequency of clk_div is one sixth of the frequency of original clk. In this example, we are going to use this clock divider to implement a signal of exactly 1 Hz frequency. First, we will need to calculate the constant. As an example, suppose the input clock frequency of the board is 100 MHz. We want our clk_div to be 1 Hz. So, it should take 100000000 clock cycles before clk_div goes to '1' and returns to '0'. In another words, it takes 50000000 clock cycles for clk_div to flip its value. So, the constant we need to choose here is 50000000.