Lab Project: Structural Design of Sequential Circuits Problem Statement Design a circuit that increments a digit (0 - F) shown on the seven-segment display device once each second. The circuit has four pushbutton inputs: one button starts the counter, a second button stops the counter, a third button increments the counter, and the fourth button asynchronously resets all memory devices in the design. The system has the block diagram shown Fig. 1 below. You must create the 4-bit counter, a clock divider, a seven-segment display decoder, and a controller circuit. You may use any design tools or methods you wish. You must also create and submit a state diagram for the controller, together with K-maps showing the next-state and output circuits in your final report. Controller 4-bit counter 7-seg decoder BTN1 Start Run Cen B0 A BTN2 Stop B BTN3 Inc C B1 Clk divider B2 D Clk pin Clk Clk B3 E RST F RST G BTN4 Figure 1. Clock divider with a counter and a comparator Clock Divider A clock signal is needed in order for sequential circuits to function. Usually, the clock signal comes from a crystal oscillator on-board. The oscillator used on Intel FPGA boards usually ranges from 50MHz. However, some peripheral controllers do not need such a high frequency to operate. We can use a counter with a comparator to condition a flip-flop with an inverter to implement a clock divider that can control the output frequency of the on-board clock, slowing it to 1Hz. The block diagram of such a clock divider is shown in Fig. 2. Counter Comparator Q A ->clk EQ rst Constant En D Q clk > Clk clk div Rst rst Figure 2. Clock divider with a counter and a comparator. In the block diagram, the counter increases by 1 whenever the rising edge of clk arrives. It also resets its output to '0' when it reaches the constant number defined in the constant block. The comparator compares the output of the counter with the pre-defined constant and asserts EQ if the output of counter is equal to the pre-defined constant. When EQ is asserted, the output of the clock divider flips. Let's assume that the pre-defined number is 3, and the output of clock divider (clk_div) is initialized to 0. It takes three clock cycles before the output of the counter equals the pre-defined constant, 3. 2 pages Lab Project #10: Structural design of Sequential Circuits When it reaches 3, the output of clock divider (clk_div) turns to 1, and the counter resets itself. It takes another three cycles before the output of the counter equals the pre-defined constant, 3. When it reaches 3 again, clk_div turns back to 0. So, it takes 6 clock cycles before clk_div goes to 1 and returns to 0 again. As a result, the frequency of clk_div is one sixth of the frequency of original clk. In this example, we are going to use this clock divider to implement a signal of exactly 1 Hz frequency. First, we will need to calculate the constant. As an example, suppose the input clock frequency of the board is 100 MHz. We want our clk_div to be 1 Hz. So, it should take 100000000 clock cycles before clk_div goes to '1' and returns to '0'. In another words, it takes 50000000 clock cycles for clk_div to flip its value. So, the constant we need to choose here is 50000000.

V. a) Sketch a 3 input NOR gate with transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter ( R). Assume all the diffusion nodes are contacted. Draw the equivalent circuit for the falling output transition and the rising output transition.

the message signal m(t) has the Fourier transform shown in Figure P-3.11(a). This signal is applied to the system shown in Figure P-3.11(b) to generate the signal y(t).The 1. Plot Y(f), the Fourier transform of y(t). 2. Show that if y(t) is transmitted, the receiver can pass it through a replica of the system shown in Figure P-3.11 (b) to obtain m(t) back. This means that this system can be used as a simple scrambler to enhance communication privacy.

4. Design a combinational circuit with inputs a, b, c, d and outputs w, x, Y, z. Assume that the inputs a, b, c, d represent a 4-bit signed number (2s complement). The output is also a signed number in which is the 2s complement of the input.

Question 5 (Programmable Logic): Tabulate the PLA programming table for the four Boolean functions listed below.Minimize the number of product terms and draw the PLA circuit. A(x, y, z)=\sum(0,1,5,7) B(x, y, z)=\sum(2,4,5,6) C(x, y, z)=\sum(0,1,2,3,4) D(x, y, z)=\sum(3,6,7)

1. Suppose we have the signal x(n) = (0.9)^n u(n-50) as input to the LTI system with impulse response h(n)= (0.8)^n u(n). a) Compute (using a for-loop) and plot the output y(n) for 0 <= n <= 100. You might want to use the MATLAB function "stem" to plot. b) Compare this to theory. c) Repeat (a-b) for h(n) = (-0.8)^n u(n).

An array of 10 isotropic elements are placed along the z-axis a distance d apart. Assum-ing uniform distribution, find the progressive phase (in degrees), half-power beam width (in degrees), first-null beam width (in degrees), first side lobe level maximum beam width (indegrees), relative side lobe level maximum (in dB), and directivity (in dB) (using equations and the computer program Directivity of Chapter 2, and compare) for (a) broadside (b) ordinary end-fire (c) Hansen-Woodyard end-fire

Figure 1 is a dimensioned plot of the steady state carrier concentrations inside a pn step junction diode maintained at room temperature. Is the diode in forward or reverse bias? Explain your answer. Does low level injec tion prevail? Explain your answer. What are the p- and n-side doping concentrations? Determine the applied voltage, VA. Determine the built-in potential, Vi- If we know this diode is made of silicon, determine the width of the depletionregion, W.

9. If a GSM timeslot consists of 6 trailing bits, 8.25 guard bits, 26 training bits, and 2 traffic bursts of 58 bits of data. Find the total number of bits in each time slot. If a frame has 8 slots, find the total number of bits in each frame, also calculate overhead bits in each frame and frame efficiency.

2. (Streetman 6th 5.24 modified) In a p+-n junction reverse biased at 10 V,the capacitance is 10 pF. If the doping of the n side is doubled and there verse bias changed to 80 V, what is the capacitance? What is the maximum doping on the n side (after doubling) that makes it possible to apply a reverse bias of 80 V in silicon? In GaAs? (see Figure 5-22)

You are required to design a sequence detector circuit which detects all non-overlapped instances of the input pattern "10110" in a string of bits coming through an input line X and generates an active high output Y when detected. ) Produce a suitably labeled Moore machine state diagram for this problem. In the design, make sure that there are no missed patterns and explain the choice of number of states, number of bits in the state representation and the choice of the next state transitions in detail. Write a truth table that tabulates the states / transitions of the sequence detector and the output signal. Derive and simplify the Boolean expressions for the next state logic and the output. Sketch and label a schematic diagram that implements your solution using D-type flip flops and your choice of logic gates. Clearly identify the key blocks of the state machine on the diagram. Sketch the timing diagram for the clock, input, current state and output signals for the following input sequence (assume the state machine is reset at the start of the sequence): 10101110110. Assume the input signal is asynchronous and make sure that you correctly align the transitions for the synchronous signals. Discuss the graphs in terms of transitions on the state diagram presented in Part (a). Demonstrate that your state machine correctly identifies the correct input pattern in the input string given.