o Design a positive edge-triggered flip- flop, and verify its operation with simulations. o Measure its current consumption, setup time, and hold time through simulation. • Turn in: ■ Flip flop

schematic ■ Test bench schematic ▪ Simulation wave form showing proper operation. This simulation should show D transitions during both CLK=1 and CLK=0 phases to show that the device is truly edge-triggered (i.e. that it does not have a transparent phase); and 1=>0 and 0=>1 output transitions on clock edges. ▪ Simulation results showing the relationship between tpc and tcq and illustrating how you determined tsetup and tpcq ▪ Simulation results showing the relationship between tcp and tcq and illustrating how you determined thold. ▪ A table showing current consumption IDD, setup time tsetup, hold time thold, and Clk-Q dolayt