SPECIFICATIONS Specified Assignment Content Design and make a circuit to that measures the pulse in your finger demonstrating the output on an oscilloscope, using Proteus software. PCB Design · The device shall be constructed on a single-sided printed-circuit board (PCB.) · The PCB must include your name, student number, and UCLan email. · If additional connections are required these shall be provided by 0Q links/wires. · The dimensions of the PCB should be no greater than 70 mm x 70 mm. Circuit Design Create a simple pulse sensor using photoplethysmography, it starts with a very low voltage signal so needs to be amplified and high frequencies and noise needs to be removed. Components o TCRT1000 Op amp LM358 Resistors and Capacitors of various sizes Voltage regulator LM7805 (if required) Power supply voltage range Regulate the power source so a safe DC value of 5 Volts is provided to the op amp circuit. Practical Work Construction Manufacture your given PCB, you will need to compare the design to your own circuit to calculate the correct format of the components. INSTRUCTIONS Tasks (keep a record in a log book though out, this is for your benefit is not required for marking) · Task 1. Research circuits and complete calculations. · Task 2. Design a circuit to meet the specification using Proteus · Task 3. Design a PCB layout for your circuit using ECAD Proteus, · Task 4. Interim Review at deadline. · Task 5. Manufacture your given PCB · Task 6 Test circuit in the laboratory, making appropriate measurements on an oscilloscope and then compare to the schematic simulation. · Task 7 Fault find circuit Power supply voltage range Regulate the power source so a safe DC value of 5 Volts is provided to the op amp circuit. Practical Work Construction Manufacture your given PCB, you will need to compare the design to your own circuit to calculate the correct format of the components. INSTRUCTIONS Tasks (keep a record in a log book though out, this is for your benefit is not required for marking) · Task 1. Research circuits and complete calculations. · Task 2. Design a circuit to meet the specification using Proteus · Task 3. Design a PCB layout for your circuit using ECAD Proteus, · Task 4. Interim Review at deadline. con PCR · Task 6 Test circuit in the laboratory, making appropriate measurements on an oscilloscope and then compare to the schematic simulation. · Task 7 Fault find circuit · Task 8 Analyse circuit, compare your results to the specifications, simulations, explain and include improvements. Provide evidence, statements, photographs, pictures of all your work in a formal Technical Presentation. Please refer to the Marking Scheme Breakdown for more details regarding assessment and tasks. Marking Scheme Breakdown Interim Review Marks 10% Demonstration of own Proteus Documents Show and explain + Schematic Diagram + Simulation + PCB Design /10 Marking Scheme Breakdown Presentation Marks 90% rks 90% 11:07 € 4G 53 ‹ Back ASS 2 Pulse Sensor intro ... Proteus. Task 3. Design a PCB layout for your circuit using ECAD Proteus. Task 4. Interim Review at deadline. Task 5. Manufacture your given PCB. Task 6. Test circuit in the laboratory, making appropriate measurements on an oscilloscope and then compare to the schematic simulation. Task 7. Fault find circuit. Task 8. Analyse circuit, compare your results to the specifications, simulations, explain and include improvements. Please refer to the Marking Scheme Breakdown for more details regarding assessment and tasks ._ Pulse Sensor Heart Rate Monitor TASK 1 Research TCRT1000 Note the TRCT1000 does not exist on Proteus so we will be using a low voltage AC signal to simulate the circuit. Passive high pass filter Op Amp LM358 Non inverting amplifier Active low pass filter Buffer Voltage Regulator LM7805 to control the supply voltage. Pulse Sensor Heart Rate Monitor Task 2. Design and simulate a circuit to meet the specification using Proteus. Refer to the block diagram provided in this presentation. Task 3. Design a PCB layout for your circuit using ECAD Proteus. ( You'll get some extra help with this so it shouldn't take so long) -

V. a) Sketch a 3 input NOR gate with transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter ( R). Assume all the diffusion nodes are contacted. Draw the equivalent circuit for the falling output transition and the rising output transition.

the message signal m(t) has the Fourier transform shown in Figure P-3.11(a). This signal is applied to the system shown in Figure P-3.11(b) to generate the signal y(t).The 1. Plot Y(f), the Fourier transform of y(t). 2. Show that if y(t) is transmitted, the receiver can pass it through a replica of the system shown in Figure P-3.11 (b) to obtain m(t) back. This means that this system can be used as a simple scrambler to enhance communication privacy.

4. Design a combinational circuit with inputs a, b, c, d and outputs w, x, Y, z. Assume that the inputs a, b, c, d represent a 4-bit signed number (2s complement). The output is also a signed number in which is the 2s complement of the input.

Question 5 (Programmable Logic): Tabulate the PLA programming table for the four Boolean functions listed below.Minimize the number of product terms and draw the PLA circuit. A(x, y, z)=\sum(0,1,5,7) B(x, y, z)=\sum(2,4,5,6) C(x, y, z)=\sum(0,1,2,3,4) D(x, y, z)=\sum(3,6,7)

1. Suppose we have the signal x(n) = (0.9)^n u(n-50) as input to the LTI system with impulse response h(n)= (0.8)^n u(n). a) Compute (using a for-loop) and plot the output y(n) for 0 <= n <= 100. You might want to use the MATLAB function "stem" to plot. b) Compare this to theory. c) Repeat (a-b) for h(n) = (-0.8)^n u(n).

An array of 10 isotropic elements are placed along the z-axis a distance d apart. Assum-ing uniform distribution, find the progressive phase (in degrees), half-power beam width (in degrees), first-null beam width (in degrees), first side lobe level maximum beam width (indegrees), relative side lobe level maximum (in dB), and directivity (in dB) (using equations and the computer program Directivity of Chapter 2, and compare) for (a) broadside (b) ordinary end-fire (c) Hansen-Woodyard end-fire

Figure 1 is a dimensioned plot of the steady state carrier concentrations inside a pn step junction diode maintained at room temperature. Is the diode in forward or reverse bias? Explain your answer. Does low level injec tion prevail? Explain your answer. What are the p- and n-side doping concentrations? Determine the applied voltage, VA. Determine the built-in potential, Vi- If we know this diode is made of silicon, determine the width of the depletionregion, W.

9. If a GSM timeslot consists of 6 trailing bits, 8.25 guard bits, 26 training bits, and 2 traffic bursts of 58 bits of data. Find the total number of bits in each time slot. If a frame has 8 slots, find the total number of bits in each frame, also calculate overhead bits in each frame and frame efficiency.

2. (Streetman 6th 5.24 modified) In a p+-n junction reverse biased at 10 V,the capacitance is 10 pF. If the doping of the n side is doubled and there verse bias changed to 80 V, what is the capacitance? What is the maximum doping on the n side (after doubling) that makes it possible to apply a reverse bias of 80 V in silicon? In GaAs? (see Figure 5-22)

You are required to design a sequence detector circuit which detects all non-overlapped instances of the input pattern "10110" in a string of bits coming through an input line X and generates an active high output Y when detected. ) Produce a suitably labeled Moore machine state diagram for this problem. In the design, make sure that there are no missed patterns and explain the choice of number of states, number of bits in the state representation and the choice of the next state transitions in detail. Write a truth table that tabulates the states / transitions of the sequence detector and the output signal. Derive and simplify the Boolean expressions for the next state logic and the output. Sketch and label a schematic diagram that implements your solution using D-type flip flops and your choice of logic gates. Clearly identify the key blocks of the state machine on the diagram. Sketch the timing diagram for the clock, input, current state and output signals for the following input sequence (assume the state machine is reset at the start of the sequence): 10101110110. Assume the input signal is asynchronous and make sure that you correctly align the transitions for the synchronous signals. Discuss the graphs in terms of transitions on the state diagram presented in Part (a). Demonstrate that your state machine correctly identifies the correct input pattern in the input string given.