Assignment 6. Write a CUDA code that parallelizes the sequential pseudo code given below so that each thread working on updating a sub-matrix of size n/p x n, where p is the total number of threads. Use multiple thread blocks and multiple threads in each block. You may assume n divisible by the total number of threads. Input: D, n x n matrix with 0 on diagonal, positive values other places Output: D /*** hbuf[n], vbuf[n]: buffers used in the code *** for k starting from 0 through n-1 for i starting from 0 through n-1 vbuf[i] = D[i] [k] end for i-loop for j starting from 0 through n−1 hbuf[j] = D[k] [j] end for j-loop for i starting from 0 through n-1 for j starting from 0 through n-1 D[i][j] end for j = min{ D[i][j], vbuf[i]+ hbuf[j] } / end for i end for k 1 p-1 1. Install CUDA on your laptop if it has Nvidia card. If no one in your group has NVidia card, merge two groups so that someone in the merged group has NVidia; or get HPCC account and get access to a queue with NVidia nodes. 2. Learn CUDA programming by finding programming tutorial online.

Ques 6 Your goal is to navigate a robot out of a maze. The robot starts in the center of the maze facing north. You can turn the robot to face north, east, south, or west. You can direct the robot to move forward a certain distance although it will stop after hitting a wall. a) Formulate this problem. This means you will have to describe initial state, goal test,successor function. and cost function. Successor function is a description of the robots successive actions after the initial state. We’ll define the coordinate system so that the center of the maze is at (0, 0), and the maze itself is a square from (-1,–1) to (1, 1)

5. (P31,In modern packet-switched networks, including the Internet, the source host segments long, application layer messages (for example, an image or a music file) into smaller packets and sends the packets into the network. The receiver then reassembles the packets back into the original message. We refer to this process as message segmentation. The figure below illustrates the end-to-end transport of a message with and without message segmentation. Consider a message that is 8 * 106 bits long that is to be sent from source to destination in the figure. Suppose each link in the figure is 2 Mbps. Ignore propagation, queuing, and processing delays. (a) Consider sending the message from source to destination without message segmentation. How long does it take to move the message from the source host to the first packet switch? Keeping in mind that each switch uses store-and-forward packet switching, what is the total time to move the message from source host to destination host? Now suppose that the message is segmented into 800 packets, with each packet being 10,000 bits long. How long does it take to move the first packet from source host to the first switch? When the first packet is being sent from the first switch to the second switch, the second packet is being sent from the source host to the first switch. At what time will the second packet be fully received at the first switch? c) How long does it take to move the file from source host to destination host when message segmentation is used? Compare this result with your answer in part (a) and comment. ) In addition to reducing delay, what are reasons to use message segmentation? e) Discuss the drawbacks of message segmentation. In addition to reducing delay, what are reasons to use message segmentation? -Discuss the drawbacks of message segmentation.

. [10 points]Suppose a process in the Host C has a UDP socket with port number 6789. Suppose both Host A and Host B each send a UDP segment to Host C with destination port number 6789. Will both of these segments be directed to the same socket at Host C? If so, how will the process at Host C know that these two segments originated from two different hosts?

A particular system is controlled by an operator through commands entered from a keyboard.The average number of commands entered in an 8-hour interval is 60. Show your work toreceive full credit. a. Suppose the CPU scans the keyboard every 100ms. How many times will the keyboard bechecked in an 8-hour period? b. By what fraction would the number of CPU visits to the keyboard be reduced if interrupt-driven 1/0 were used?

22. Many CPU-scheduling algorithms are parameterized. For example, the RR algorithm requires a parameter to indicate the time slice. Multilevel feedback queues require parameters to define the number of queues, the scheduling algorithms for each queue, the criteria used to move processes between queues, and so on. These algorithms are thus really sets of algorithms (for example, the set of RR algorithms for all time slices, and so on). One set of algorithms may include another (for example, the FCFS algorithm is the RR algorithm with an infinite time quantum). What (if any) relation holds between the following pairs of algorithm sets? a. Priority and SJF b. Multilevel feedback queues and FCFS c. Priority and FCFS

23. Suppose that a CPU scheduling algorithm favors those processes that have used the least processor time in the recent past. Why will this algorithm favor I/O-bound programs and yet notpermanently starve CPU-bound programs?

1) In a computer instruction format, the instruction length is 11 bits and the size of an address field is 4 bits. Is it possible to have: 5 two-address instructions 45 one-address instructions 32 zero-address instructions using the specified format? Justify your answer. b) Assume that a computer architect has already designed 6 two-address and 24 zero address instructions using the instruction format above. What is the maximum number of one-address instructions that can be added to the instruction set?

(1) In a computer system, memory operations currently take up 30% of execution time. A new gadget called a cache (i.e. an L1 cache) speeds-up 80% of the memory operations by a factor of 4. What is the speed-up due to the cache? ) [5] A second new gadget called an L2 cache speeds-up half the remaining20% of the memory operations by a factor of 2. What is the total speed-up with the L1 and L2 cache together?

client, and there is no other traffic on this path. Assume each packet of size L bits, and both links have the samepropagation delay dprop- (a) What is the packet inter-arrival time at the destination? That is, how much time elapses from when the lastbit of the first packet arrives until the last bit of the second packet arrives? (b) Now assume that the second link is the bottleneck link (i.e., RcjRs). Is it possible that the second packetqueues at the input queue of the second link? Explain. Now suppose that the server sends the second packetT seconds after sending the first packet. How large must T be to ensure no queuing before the second link?Explain. Consider the figure (a) below. Assume that we know the bottleneck link along the path from the server to theclient is the first link with rate Rs bits/sec. Suppose we send a pair of packets back to back from the server to the

Let a denote the rate of packets arriving at a link in packets/sec, and let µ denote the links transmission rate in packets/sec. Based on the formula for the total delay (i.e., the queuing delay plus the transmission delay) derived in the previous problem, derive a formula for the total delay in terms of a and µ. Note that the link's transmission rate in packet/sec is R/L.