Preparation before the lab*

Question 8. With a bus clock at 80 MHz, the slowest we can run SysTick interrupts is80,000,000/16777216=4.768 Hz. How could we sample at 1 Hz (trigger ADC exactly every 1sec)?Give a flow chart including a mailbox used to pass data to the foreground.

2. Figure shows four switches that are part of the control circuitry in a copy machine. The switches are at various points along the path of the copy paper as the paper passes through the machine. Each switch is normally open, and as the paper passes over a switch, the switch closes. It is impossible for switches SW1 and SW4 to be closed at the same time. Design the logic circuit to produce a HIGH output whenever two or more switches are closed at the same time. Use K mapping and take advantage of the don't-care conditions. SW1 SW2 SW3 SW4 41 w +5V +5V +5V +5V Logic circuit X HIGH whenever two or more switches are closed* *SW1 and SW4 will never be closed at the same time

7. The circuit shown in the Figure is a 4-bit circuit that can add or subtract numbers in a form used in computers (positive numbers in true form; negative numbers in complement form). a) Explain what happens when the Add /Subt. input is HIGH. b) What happens when Add /Subt. is LOW? Add/Subt, O A₂ B₂ A B C Ca Σ Σ₂ A₂ B₂ B C Coat Σ A, B₁ BC M 144 A Bo Ca 194 5

6. BCD numbers are applied sequentially to the BCD-to-decimal decoder in the Figure. Draw a timing diagram, showing each output in the proper relationship with the others and with the inputs. BCDV/DBC 2 7419042 20 7

2.3 Simplify each of the following expressions by applying one of the theorems. State the theorem used. (a) X'Y'Z + (X'Y'Z)' (c) ACF + AC'F (e) (A'B + C + D)(A'B + D) (b) (AB' + CD) (B'E + CD) (d) A(C+ D'B) + A' (f) (A + BC) + (DE + F)(A + BC)'

1. A Trojan writer must ensure that his/her Trojan circuitry is not likely to be detected during manufacturing test, and thus understanding how test works is important. Consider the following circuit.

2. For each of the following expressions, construct the corresponding logic circuit, using AND and OR gates and INVERTERS. (a) x = AB(C+D) (b) z = A+B+CDE + BCD (α) x= AB(C+0) A+B+CDE + BCD Ao 3 De A 8 X

Implement in functional level Verilog a state machine that will generate the pulse sequences shown in Figure Q1. The state machine has two outputsZ1 and Z2. Output pulse streams can be selected using four different input states I=0 to l=4. You may assume that you have a clock pulse of the required period. Implement a module in Function level Verilog that would generate the correct next state sequence based on the given input conditions. You do not need to generate the output sequence.

5. Show the decoding logic for each of the following codes if an active-HIGH (1) output is required: (d) 11100 (c) 11011 (g) 000101 (h) 1110110 (a) 1101 (e) 101010 (b) 1000 (f) 111110

3. How long would it take to exhaustively test a 64-bit adder (assuming no carry-in) if tests are applied at 1 GHz? If we do this, are we guaranteed to have detected all the Trojans that could be present?