Implement in functional level Verilog a state machine that will generate the pulse sequences shown in Figure Q1. The state machine has two outputsZ1 and Z2. Output pulse streams can

be selected using four different input states I=0 to l=4. You may assume that you have a clock pulse of the required period. Implement a module in Function level Verilog that would generate the correct next state sequence based on the given input conditions. You do not need to generate the output sequence.