the logic effort of n input nand is n23 and parasitic delay of n input
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III. Consider the two designs of CMOS gate shown in the following Figure. 1) Give an intuitive argument about which will be faster. 2) Calculate the path effort, delay and
input capacitances x and y to achieve Lowest delay with the approach (a) and (b). The logic effort of n input NAND is (n+2)/3 and parasitic delay of n input NAND is n.