This homework requires you to design and implement the Duke 250/16, a 16-bit MIPS-like, word- addressed (not byte-addressed) RISC architecture. (A word is 16-bits.) We have specified the architecture, and you

will use Logisim to design a single cycle implementation of this architecture. The architecture's instructions are specified in Table 1. Submission instructions - please read VERY carefully: You must do all work individually, and you must submit your work electronically via GradeScope. • You will submit a Logisim file called cpu.circ. This file is the circuit for your processor. . ● If your CPU is failing one or more tests, you are encouraged to submit a PDF file called cpu.pdf. This file is your description of your processor, and the grading TA will use this description to help assign partial credit. (This file is for your benefit!) The file should explain the following issues: o What parts of your processor work and which parts do not work. This helps us to find partial credit. o For subcircuits (e.g., register file or ALU), explain their interfaces so that we can possibly test them individually. • Non-functioning CPUs will receive partial credit of 10 points plus incremental credit for functioning subcircuits (up to 70 points); this credit will be guided by your cpu.pdf write-up. • All submitted circuits will be tested for suspicious similarities to other circuits, and the test will uncover cheating, even if it is "hidden." Plagiarism of Logisim code will be treated as academic misconduct. • Logisim implementations must use only the components specified in the "Logisim restrictions" section later in this document. For successful automated grading, your circuit must meet the requirements specified in the "Automated testing" section. • You may not use any pre-existing Logisim circuits (i.e., that you could possibly find by searching the internet).