Which of the following is not included in the five-number summary of box-and whisker plot?

V. a) Sketch a 3 input NOR gate with transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter ( R). Assume all the diffusion nodes are contacted. Draw the equivalent circuit for the falling output transition and the rising output transition.

4. Design a combinational circuit with inputs a, b, c, d and outputs w, x, Y, z. Assume that the inputs a, b, c, d represent a 4-bit signed number (2s complement). The output is also a signed number in which is the 2s complement of the input.

Question 5 (Programmable Logic): Tabulate the PLA programming table for the four Boolean functions listed below.Minimize the number of product terms and draw the PLA circuit. A(x, y, z)=\sum(0,1,5,7) B(x, y, z)=\sum(2,4,5,6) C(x, y, z)=\sum(0,1,2,3,4) D(x, y, z)=\sum(3,6,7)

You are required to design a sequence detector circuit which detects all non-overlapped instances of the input pattern "10110" in a string of bits coming through an input line X and generates an active high output Y when detected. ) Produce a suitably labeled Moore machine state diagram for this problem. In the design, make sure that there are no missed patterns and explain the choice of number of states, number of bits in the state representation and the choice of the next state transitions in detail. Write a truth table that tabulates the states / transitions of the sequence detector and the output signal. Derive and simplify the Boolean expressions for the next state logic and the output. Sketch and label a schematic diagram that implements your solution using D-type flip flops and your choice of logic gates. Clearly identify the key blocks of the state machine on the diagram. Sketch the timing diagram for the clock, input, current state and output signals for the following input sequence (assume the state machine is reset at the start of the sequence): 10101110110. Assume the input signal is asynchronous and make sure that you correctly align the transitions for the synchronous signals. Discuss the graphs in terms of transitions on the state diagram presented in Part (a). Demonstrate that your state machine correctly identifies the correct input pattern in the input string given.

B) In a system on a chip with 1 billion transistors, the subthreshold leakage of OFF transistors for off transistors is 100nA/um for a low threshold devices and 10nA/um for high threshold devices. The gate leakage is 5nA/um. Junction leakage is negligible. Memories use low- leakage devices everywhere. Logic uses low-leakage device in all but 5% of the paths that are most critical performance.The process used is 1.2 V - 65 nm, n =25 nm, 100 million transistors are in logic gates and rest in memory arrays. The average logic transistor width is 12% and the average memory transistor width is 4 2. The memory arrays are divided into banks and only the necessary bank is activated so the memory activity factor is 0.02. The static CMOS logic gates have an average activity factor of 0.1. Each transistor contributes 1 fF/um of gate capacitance and 0.8 fF/um of diffusion capacitance. a) Estimate the switching power when operating at 1 GHz frequency. b) Estimate static power consumption.

9. Specify the 16-bit control word that must be applied to the data path of P 11 to implement each of the following microoperations: (a) R3 - Data in (h) R4 + (0 (c) R1 - sr R4 (d) R3 - R3 + 1 (c) R2 - sl R2 (f) R1 - R2 O R4 (g) R7 - R1 + R3 (h) R4 - R5 - Constant in

1. Phosphorous donor atoms at a concentration of 10^16 cm^-3 are distributed uniformly throughout a Si sample, The material is 1 um long and area 0.1 um^2 . The electron mobility is 1250 cm^2/Vs. a. Compute the resistivity and resistance of this sample at room temperature. Use cm in your calculations and units for final answer. [10 points] b. Is this a P type or N type semiconductor? Justify. How does the resistance R change with temperature? [2+2 points]

(subtract)Inputs X; and Y, of each full adder in an arithmetic circuit have digital logic specified by the Boolean functions X_{\mathrm{i}}=A_{\mathrm{i}} \quad Y_{\mathrm{i}}=\bar{B}_{\mathrm{i}} S+B_{\mathrm{i}} \bar{C}_{\mathrm{in}} where S is a selection variable, C is the input carry, and A, and B, are input data for stage i. (a) Draw the logic diagram for the 4-bit circuit, using full adders and multiplexers. (b) Determine the arithmetic operation performed for each of the four combinations of S and C: 00,01,10, and 11.

8. Use the Boolean functions developed in problem #2 to create a circuit in verilog HDL with three inputs(x,y,z) and four outputs (a,b,c,d) with each output equal to the result of problem #2. Show your HDLcode as well as the simulation results.

[15] Use Laplace transform to solve the following differential equations (i.e.,solve for y(t)) \frac{d^{2} y}{d t^{2}}+3 \frac{d y}{d t}-4 y=e^{-t} u(t) \text { with } y(0)=I \text { and } \frac{d y(0)}{d t}=0 \frac{d^{2} y}{d t^{2}}+6 \frac{d y}{d t}+25 y=\frac{d x}{d t}+2 x \text { where } x(t)=25 u(t) \text { and ICs are } y(0)=1 \text { and } \frac{d y(0)}{d t}=1 \text { c. } D^{2} y(t)+D y(t)+2 y(t)=x(t) \text { where } x(t)=2 u(t) \text { and ICs are zero }