3-13. The half-wave rectifier with a freewheeling diode (Fig. 3-7a) has R = 122 and

Task 2: Single-phase half-wave phase-controlled rectifier with RL load Recall Chapter 2, Make a new project. Build a single-phase half-wave phase-controlled rectifier with RL load Use the sinusoidal source in the SOURCE lib set amplitude 450V and frequency 20Hz Use the pulse voltage source in the PSpice Component and set the rising time lus, falling time /us, pulse width 100μs, low-side output voltage OV, and high-side output voltage 201 Use the load parts in the PSpice Component set resistor 50, and inductor 20mH in series. Use the thyristor in the ELEC4174_Fall_2023 library. Use the time domain simulation set up, set run to time as 50ms and maximum step size as le a. Show your schematic. b. If we have voltage pulse (gate signal) appears at 15ms, 1) Plot the voltage across the resistor and voltage across the inductor. 2) Find the conduction angle (approximately) using results in part b.1). 3) Evaluate your plots in part b.1) for maximum value for VR and the point when V₁ across 0, briefly explain with words or equations what happened there.

Instruction: Use any circuit simulation tool to answer the problems below. 1. A BJT differential amplifier is biased from a 2-mA constant-current source and includes a 100-2 resistor in each emitter. The collectors are connected to +10 V via 5 k resistors. A differential input signal of 0.1 V is applied between the two bases. Assume that the transistors are matched and have ß-100 and Is=14 fA. (a) With the aid of LTSpice (or any other circuit simulation tool), determine the signal current in the emitters i, and the base-emitter voltage vibe for each BJT. (b) What is the total emitter current in each BJT? (c) What is the signal voltage at each collector? (d) What is the voltage gain realized when the output is taken between the two collectors? R₁ = 5 ΚΩ Q₁ +5 V -5 V 2 mA Q2 02 R₂ = 5 ΚΩ Vi Ri Vcc = +10 V 150 150 Ω 0.5 mA 20 ΚΩ

6. Turning the output signal into a DC signal Provide some method of turning your output waveform from (4) into a DC signal. If not perfectly DC, then at least an oscillating signal, not necessarily sinusoidal, that has a ripple voltage of 99-101 mV. Assume all the same parameters: 12 V amplitude, 60 Hz, 1 kOhm load. Hint: RC decay. Simulate your new full circuit in LTSPICE and estimate the additional cost, assuming we want to finish the same total number of circuits as in (5). SPICE plots and Digikey screenshots are needed here.

5. Secondary choice of diode through cost considerations Look up your chosen diode on www.digikey.com. Suppose we make one bulk purchase and make all the bridge rectifiers we can out of it. How many circuits can we build, and how much do the diodes cost? Are there any cheaper alternatives that would still work? Provide cost estimates from the Digikey website. Digikey screenshots are needed here.

To complete the initial introduction to Elvis sections (parts A, B &C) of the lab no pre-laboratory exercise is required. Please complete the following pre-laboratory exercises. 1. (3pts) For the circuit shown in Fig. 2, derive the transfer function for Vo/Vin in terms of R, C and find the expressions for the magnitude and phase responses. Express your results in the form Vo Vin Vin(t) jw Wp jw Wp Where wpid the pole frequency location in rad/sec 1+ C He R Vo(t) Fig. 2. First order high pass filter (integrator) 2. (3pts) For C= 10nF, find R so that pole frequency location is 4.8 kHz. Draw the bode (magnitude and phase) plots using MATLAB, Python or Excel. 3. (4pts) Simulate the high pass filter circuit using the PSpice simulator (Capture CIS 17.4 ). Compare the simulation results with your hand-calculation. Attach the magnitude and phase simulation results and compare them with part 2 results (bode plots).

1) Generate the Ip vs Vps plots within the power supply limits of 0-3V, do this for gate- source voltages between zero and 3V spaced by 0.5 volts for both our default NFET and our PFET (W/L-5/0.5). This covers the full operating range of our devices. Label each trace with the VGs voltage used for each curve. For the NFET your plot should look qualitatively like this: 104 VGSI-VTH Saturation Region HLA-ESDA HLA-ESDA Vass Vosz Vast To do this you need to use a DC parameterized sweep with two loops, in one loop you are sweeping VDs and the other you are stepping VGs. To get the PFET characteristic to look like this you will need to change the signs of the some of the voltages and currents. b) Plots of the simulation results Repeat for the PFET Vos Careful: getting the PFET scans is trickier than you think, be sure that you cover the triode and saturation regions. (need the screenshots for these) Questions: For the NFET a) A legible copy of your simulation schematic, make sure it shows the device length and width a) For similar absolute values of the bias voltages the PFET and NFET drain currents are different, why? b) Observe how the slope of the curves in saturation change for different Vos. What does this imply about ro, the small signal output resistance as a function of Ves? c) What would the maximum current be if instead of a 5 micron wide device you had a 20 micron wide device?

Task 1: Three-phase half-wave diode rectifier with R load Recall Chapter 1, Make a new project. Build a three-phase half-wave diode rectifier with R load. Use the sinusoidal source in the SOURCE lib set amplitude 110V and frequency 60Hz. Use the diode and load parts in the PSpice Component set resistor 5.2. Use the time domain simulation set up, set run to time as 50ms and maximum step size as le¹³. a. Show your analysis tab of simulation settings. b. Plot the load current. c. If we want to simulate an open circuit error happening at source phase a (0 deg shift) for this rectifier, 1) Show your modified schematic for this new simulation. 2) Plot the load current again. 3) Compare your answer for part c.2) with part b, briefly explain your plots.

Report Show that all transistors in the circuits operate properly and in the expected modes. Show that circuits can operate without distortion. Show the gain, and if possible, the BW of the circuits. Be prepared to discuss affects of the capacitors. Compare the two versions of the Op Amp. Explain why the various results differ, or if they do not differ, why they can differ.

2) Next generate a plot for Ip vs Vos for the diode connected NFET over 0-3 V of VDS bias. Include on your plot the effect of a bulk voltage of -0.5, 0, 0.5 and 1V. The easiest way to get all 3 curves on the same plot is to use 3 instances of the device in your simulation schematic, each with different bulk bias voltages. Using NET aliases can be useful here. Repeat for our PFET but now with bulk bias voltages of 3.5, 3, 2.5 and 2V. Here you should clearly see the body effect on the transistor characteristic. Replot these for the square root of ID vs VGs and estimate the effective threshold for each bulk voltage. For the NFET a) Schematic used for the simulation b) Plot showing the simulation results for ID vs VGs for the different bulk voltages. c) Plot of the square root of ID vs VGS for the different bulk voltages. d) A table showing the threshold voltages vs the bulk bias Then include the same for the PFET. (need the screenshots for these) General observations and suggestions: be sure you have a proper ground or the simulator will not work, it needs to be set as node zero. Setting the bias will be a challenge for many of you. Think about the meaning of the sign of the current. To make the PFET plots look "normal" you can change the signs of the voltages and currents plotted as appropriate. Use enough points in your simulation to make the curves look smooth. Note: clearly label the axes, label the traces with the Vgs or bulk bias voltages used, also make the traces thicker than the default and adjust colors for readability. Be careful in your choice of NFET3 or NFET4, only use the 3 terminal version if you are sure that the source voltage will always be at ground for the NFET. The NFET3 and PFET3 versions have their source and bulk terminals tied together internally. For our process this cannot be done for the NFET but it can for the PFET.

To complete the initial introduction to Elvis sections (parts A, B &C) of the lab no pre-laboratory exercise is required. Please complete the following pre-laboratory exercises. 1. (3pts) For the circuit shown in Fig. 2, derive the transfer function for Vo/Vin in terms of R, C and find the expressions for the magnitude and phase responses. Express your results in the form Vo Vin Vin(t) jw Wp jw Wp Where wpid the pole frequency location in rad/sec 1+ C He R Vo(t) Fig. 2. First order high pass filter (integrator) 2. (3pts) For C= 10nF, find R so that pole frequency location is 4.8 kHz. Draw the bode (magnitude and phase) plots using MATLAB, Python or Excel. 3. (4pts) Simulate the high pass filter circuit using the PSpice simulator (Capture CIS 17.4 ). Compare the simulation results with your hand-calculation. Attach the magnitude and phase simulation results and compare them with part 2 results (bode plots).