Question 5 (40 points):

Consider the following Circuit. Assume timings for both D flip-flops are identical, and they are:

t=0

f

New

Data

Input

Clock

D

DFF-1

DFF

►C

Q1

Combinational

Logic

Td =Time delay

Wire Delay

D2

DFF-2

DFF

DC

Q*b

D-Flip-flop Setup time = T₁= 15 psec

• D-Flip-flop Hold time = T₁ = 20 psec

• D-Flip-flop Clock-to-Q delay = To = 83 psec

• Combinational Logic Delay = T₁ = 35 psec

a) Compute the new data input uncertainty time interval (aperture time T₁).

b) How long does it take for D-Flip-flip to process each new data?

Out

c) What is the earliest time that the rising edge of clock can be asserted for the new input

data to be processed by DFF- 1?/nd) What is the earliest time that the output data of the first flip-flop, DFF-1, is valid at the input

of the combinational logic?

e) If there is no wire delay, what is the minimum clock period?

f) What is the maximum acceptable wire delay (Clock Skew)?