Analog Electronics

Problem 6: Consider the circuit shown in Figure 6. Do not ignore channel length modulation. (a) Calculate the input impedance. (b) Calculate the gain, Vout/Vin. (3 + 7 = 10 points) Rs Vin X M 모품 MI Figure 6 Val Vout

4. Assume that an observer calculates electric field and potential by measuring the force on a test charge. This observer moves along the path described by the green arrow. Finally, assume the system is in vacuum. (a) Plot and justify |E| for a charged sphere-Q enclosed within an ungrounded spherical metal shell. (b) Draw all relevant field lines on the schematic (within reason). Hint: consider where the charges would be induced on the inner and outer surfaces of the shell.

Lab 5: Design of a DC Power Supply Learning objectives: - To design, build and test a DC power supply (PS), which converts AC voltage to DC voltage. - To understand the technical trade-offs involved in the design of a DC PS. - To apply engineering reasoning in the process of evaluating design options. - To practise the language of technical argument and reasoning - being succinct, accurate and coherent. - To understand the purpose of the specification of requirements (SoR) - To understand the principles of testing against a SoR Each lab in this module helps you complete one part of the analysis and calculations needed for the DC power supply design in this lab. You are therefore expected to compile the necessary preparation work as you progress through the labs. DESIGN TASK: Your task is to design a power supply circuit (comprising a rectifier with a reservoir capacitor, and a regulator) that can be mounted as a daughter-board module on the main circuit board for which the regulated power supply is required. The input to the module is the low AC voltage with 12V rms, 50Hz. The signal is generated by the AC to AC adaptor as shown in Figure 1. A pair of 4mm cable test sockets is utilized to feed out the signal to a breadboard. The fuse will blow in the event of a high current, removing power from the power supply circuit.

Problem 4. (30 points) Single-stage amplifier frequency response calculation (a) What is DC value of Vdc,in and Vdc,out? (b) Capacitance analysis of M1: Calculate CGS1, CGD,1, CDB1. (c) Capacitance analysis of M2: Calculate CGs,2, CSB,2. (d) What is the small-signal representation for M2. (e) What is the small-signal model for the whole amplifier. (f) What is small-signal gain A, = Vout/Vin at DC? (g) What is the dominant pole for the amplifier (Note: remember to simplify analysis by adding capacitors that appear in parallel in the small-signal model). What is w3dB? (h) Plot the Bode plot (magnitude and phase) for the amplifier gain, A. (please make the usual approximations).

Problem 4. (30 points) Single-stage amplifier frequency response calculation (a) What is DC value of Vdc,in and Vdc,out? (b) Capacitance analysis of M1: Calculate CGS1, CGD,1, CDB1. (c) Capacitance analysis of M2: Calculate CGs,2, CSB,2. (d) What is the small-signal representation for M2. (e) What is the small-signal model for the whole amplifier. (f) What is small-signal gain A, = Vout/Vin at DC? (g) What is the dominant pole for the amplifier (Note: remember to simplify analysis by adding capacitors that appear in parallel in the small-signal model). What is w3dB? (h) Plot the Bode plot (magnitude and phase) for the amplifier gain, A. (please make the usual approximations).

Problem 3. Single-stage amplifier frequency response (a) What are DC bias values: Vdc,in and Vdc,out? (b) Capacitance analysis of M1: Calculate CGS1, CGD,1, CDB1. (c) What is the small-signal model for the whole amplifier? (d) What is small-signal gain A, = Vout/Vin at DC? (e) What is the dominant pole for the amplifier. What is w3dB? (f) Plot the Bode plot (magnitude and phase) for the amplifier gain, A. (please make the usual approximations).

Problem 2. (10 points) NFET capacitance calculation In Fig. 3, assume Cox = 1fF/pm², C, = 0.1fF/μm², Cisw = Cov (also called CGDO and Caso) = 0.1fF/μm, W = 50µm, L= 0.5μm, E = 1pm. Assume all devices are in saturation Consider the transistor "layout" in Fig. 2. Calculate CGS, CGD, CDB, CSB.