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Given: 150kVA 2400V/240V 60 Hz transformer. Open circuit test on the 240V winding of the transformer gives: o VocO= 240V loc = 16.75A Poc=580 Watts Short circuit test was done with the low voltage winding short circuited. Vsc= 63V Isc= 62.5A Psc = 1600 Watts Exciting admittance, conductance, and susceptance. Equiva
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Figure 1 is a dimensioned plot of the steady state carrier concentrations inside a pn step junction diode maintained at room temperature. Is the diode in forward or reverse bias? Explain your answer. Does low level injec tion prevail? Explain your answer. What are the p- and n-side doping concentrations? Determine the applied voltage, VA. Determine the built-in potential, Vi- If we know this diode is made of silicon, determine the width of the depletionregion, W.

2. (Streetman 6th 5.24 modified) In a p+-n junction reverse biased at 10 V,the capacitance is 10 pF. If the doping of the n side is doubled and there verse bias changed to 80 V, what is the capacitance? What is the maximum doping on the n side (after doubling) that makes it possible to apply a reverse bias of 80 V in silicon? In GaAs? (see Figure 5-22)

1. Semiconductor and Metal-Semiconductor Interface: (a) Sketch the band diagram of a p-type doped GaAs substrate with a dopingconcentration of 1 x 1017 cm3. Calculate the position of Fermi level EF with respectto the intrinsic energy level E; assuming Boltzmann statistics. In the sketch, clearlyindicate the conduction and valence bands, the intrinsic energy level, the position ofthe Fermi level with respect to the intrinsic energy level, and the bandgap energywith its value in electronvolts. (b) How would the position of Fermi level EF with respect to the intrinsic energy level E; change, if instead of Boltzmann statistics, Fermi-Dirac statistics were used? (c) Sketch the band diagram of a metal-semiconductor interface for the contactwhich has a Schottky barrier at the interface assuming the semiconductor material isdoped n-type. (d) Also sketch the band diagram of a metal-semiconductor interface for the contactwhich is considered to be Ohmic (e) Write a comparison of the two contact interfaces and explain the differences observed in l-V characteristics obtained from measurements from these two types of metal contacts in no more than 100 words.

45. In order to design an underwater vehicle that has the characteristics of both a long-range transit vehicle(torpedo-like) and a highly maneuverable low-speed vehicle(boxlike), researchers have developed a thruster that mimics that of squid jet locomotion (Krieg, 2008). It has been demonstrated there that the average normalized thrust due to a command step input, U (s)=Tref/s given by: T(t)=T_{r e f}\left(1-e^{-\lambda t}\right)+a \sin (2 \pi f t) where Tref is the reference or desired thrust, A is the system's damping constant, a is the amplitude of the oscillation caused by the pumping action of the actuator, f is the actuator frequency, and T(t) is the average resulting normalized thrust. Find the T(s)/U(s) . Show thruster's transfer function all steps.

Problem 7 - Consider a metal-semiconductor junction that behaves according to ideal Schottky theory. Assume that the work function of a n-type semiconductor is 4.5 ev. Sketch band diagram for cases where the metal work-function is (a) 4.0 ev (b) 4.5 ev (c) 5.0 ev

6. Determine the range of Vi that will maintain VL = 9 V and not exceed the maximum power of the zener diode (PD = 450 m W) in Figure 5. What is the minimum power rating of each resistor.

Figure B3a shows a data exchange system that uses a single-bit shared bus line(SB) to pass digital information from a set of data transmitters, 'AQA3 and CO..C3',to data receivers 'B0..B3 and DO.D3'. All signals are 1-bit, apart from SA, SB, SCand SD, which are 2-bit (indicated by the 'x' enclosed within the terminal symbols). The two multiplexers (MUXS) at top-left and bottom-right of Fig. B3a use 2-bit select inputs 'SA' and 'SC' to choose a transmit channel (03). Similarly, the two de-multiplexers (DMXS) at top-right and bottom-left of Fig. B3a use 2-bit select inputs"SB' and 'SD' to choose a receive channel (03). Choose either the MUX or DMX and sketch a gate-level logic circuit implementation of the symbol (MUX or DMX). Depending upon which choice you made above, write down the Verilog-HDL description of the other symbol, Le if you sketched the logic circuit for the MUX (DMX), write down the Verilog description of the DMX (MUX). In your descriptions, you may make use of continuous assignment statements and/or primitive gate instantiations.(6 morke) Write down the name of the Verilog-HDL built-in primitive element that could be used to model the four three-state buffers connected to the shared bus 'SB', in Fig. B3a. Write down the values, in Verilog format, of the following control signals: SA, SB, SC, SD, ENA and ENB In order to perform the following data transfer operations in Fig. B3a: i.Transmit data from A3 to B1. Figure B3b shows a particular type of counter based on a shift register. The asynchronous set (S) and reset (R) inputs of the flip-flops are active-high, assume any unconnected inputs are at logic-0. (2 marks)Sketch a set of digital waveforms for the outputs, <Q3, Q2, Q1, Q0>, of the counteralong with the clock input 'CIK. Assume the circuit has previously been reset bypulsing the Rst input to logic-1. (6 marks)Given that the frequency of the clock input 'Çlk' is 10 MHz, deduce the frequency of any Q output.

IV. a) Sketch a 3-input NOR gate with transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter( R). Annotate the gate width with its gate and diffusion capacitances. Assume all diffusion nodes are contacted. b) Sketch equivalent circuits for the falling output transition. c) Sketch the equivalent circuit for worst case rising output transition. d) If R is the resistance of unit nMOS transistor and C is its capacitance, findTpdf and Tpdr for 3-input NOR gate if the output is loaded with 5 identicalNAND gates. 2) An output pad contains a chain of inverters to drive the large off-chip capacitance. If the off chip capacitance is 20pF and the first inverter has a capacitance of 40fF, how many inverters are needed to drive the load with least delay? Estimate this delay.

5. Dipole Moment on PEC Sphere (30 pts): Consider a perfectly conducting spherical ball centered at the origin of a spherical coordinate system. The sphere has radius a, and is immersed in an external electric field given by Eext =Eext Z. a) Find an expression for the external potential Vext associated with the external electric field using spherical coordinates. (*Hint: First do this in Cartesian coordinates and then convert to spherical coordinates). b) Assume the total potential is the sum of the external and induced potentials V =Vext + Vind. Write down the differential equation that governs this potential and the associate boundary conditions (*Hint: There is no o dependence and the tangential component of the electric field must be 0 on the surface of the sphere). \text { c) Show that if } V_{\text {ind }}=\frac{A \cos (\theta)}{r^{2}}, \text { the total potential satisfies the boundary } conditions and also satisfies Laplace's equation. What is the value of A? d) Find an expression for the total electric field (Eext + Eind). Show that the total field is the sum of the external field plus the fields due to an electric dipole. What is the electric dipole moment p? (*Hint: See expression of electric dipole fields from HW 3). e) Sketch the electric field lines outside of the sphere.

Consider a silicon p*-n diode with a step junction doping profile. The doping concentration on the n-side is equal to 10(14)/cm(3) and the doping concentration on the p-side is equal to 10 (17)/cm(3) . The minority carrier lifetimes are 10(-6) s. Assume room temperature for this problem. If the junction capacitance at a reverse bias voltage of 0.5V is equal to 9pF, what is the junction capacitance at the zero bias? If this diode is switched from a forward bias with a current of 3mA to the reverse biased voltage (0.5V) applied through a 500 N, what is the storage time ?If the diode is switched back to forward bias, what is the VoN value? (Hint:Io-5.57 x 10-14). Could you have solved for the Io value in part e by knowing this is a silicon p*-n diode and knowing the doping concentrations? what additional information, if any, would you have needed? If the diode is switched back to forward bias, what is the VoN value? (Hint:Jo-5.57 x 10-14)